VHDLwhiz Generic List Of Protected Type App User Guide

June 13, 2024
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VHDL package: Generic list of protected type

Generic List Of Protected Type App

Version: 1.0.1
Date: 02-Mar-22
Product URL: <https://vhdlwhiz.com/product/vhdl-package-generic-list-

ofprotected-type>
Contact email:| jonas@vhdlwhiz.com

This document describes how to use VHDLwhiz’s generic list VHDL package to store any data type in the simulator’s dynamic memory.

License

The MIT license covers the source code’s copyright requirements and terms of use.
Refer to the LICENSE.txt file in the Zip file for details.

Changelog

These changes refer to the project files, and this document is updated accordingly.

Version Remarks
1.0.0 Initial release
1.0.1 Adding this user guide to the Zip (no code changes)

Description

The linked-list implementation in this package can store any data type in the simulator’s dynamic memory. It mimics the behavior of Python’s list class and supports positive and negative indexing.
The list is unidirectional, and you can read from, insert at, or delete any element.
But if you use the shorthand append(data : data_type) procedure, it will add the new data to the highest index.
In that case, the oldest element is accessible as element number 0, while the newest element is at element -1. The negative indexing makes it easy to read from the list’s end, even as it grows.
Consequently, index 1 would refer to the second oldest element and -2 to the second newest. Any element in the list can be indexed from either end.
Refer to the comments above each method prototype for a description of each subprogram, its parameters, and return values.
Compile the list using VHDL-2008 or newer because older language revisions don’t support package generics.

Example use cases

You cannot import the generic_list.vhd file directly where you want to use it, and that’s because it uses package generics that must be mapped to a data type.
First, create a new VHDL file that specifies the data type that the list shall store.
Then you can import that VHDL package in your testbench to use it.
To store text strings, for example, first create a new VHDL file named string_list.vhd containing the following code:

VHDLwhiz Generic List Of Protected Type App - Example use
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Then, import the string_list.vhd file in your main testbench and create an instance of it like this:

VHDLwhiz Generic List Of Protected Type App - Example use cases
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The Zip contains more examples of lists that store other data types.

FIFO behavior

You can achieve a FIFO (first-in, first-out) behavior by using list. append(data) to push and list. get(0) followed by list. delete(0) to fetch the oldest element from the the list:

VHDLwhiz Generic List Of Protected Type App - Example use cases
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VHDLwhiz Generic List Of Protected Type App - Example use cases
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Note that the list protected type doesn’t have a pop() method like Python’s list class. That’s because language revisions prior to VHDL-2008 don’t have garbage collection. We must delete the elements after using them to prevent memory leaks.

LIFO behavior

To implement a LIFO (last-in, first-out), also known as a stack, you can simply read from index -1 to always get the newest element:

VHDLwhiz Generic List Of Protected Type App - Example use cases
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Method prototypes

The code listing below shows the declarative region of the generic_list.vhd package.

VHDLwhiz Generic List Of Protected Type App - Example use cases
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Zip File Content

├── Binary file RW packages – User Manual.pdf This document
├── generic_list_tb.vhd Self-checking testbench for the generic list
├── generic_list.vhd The generic list package
├── How to run.gif Screencast showing how to run the testbench
├── integer_list.vhd List of integer type package
├── LICENSE.txt License agreement
├── project.mpf ModelSim/Questa project
├── real_list.vhd List of real type package
├── run.do ModelSim/Questa script for running the testbench
├── slv8_list.vhd List of bytes (std_logic_vector) package
└── string_list.vhd List of string type package

Simulating the design

There is a self-checking testbench in the Zip file (generic_list_tb.vhd).
The VHDL testbench should work in any capable VHDL simulator supporting the full VHDL-2008 revision, but the provided run.do script only works in ModelSim/Questa.
To run the testbench, open ModelSim/Questa and type in the simulator console: do /run.do runtb

Known Issues

The generic list is unsynthesizable and only meant for simulation/testbenches.

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References

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