VHDLwhiz AXI-Style UART Modules User Manual

VHDLwhiz.com
AXI-Style UART Modules
User Manual

AXI-Style UART Modules

This document describes how to use VHDLwhiz’s general-purpose, AXI-compatible, universal asynchronous receiver-transmitter (UART) VHDL modules.

License

The MIT license covers the source code’s copyright requirements and terms of use.
Refer to the LICENSE.txt file in the Zip file for details.

Changelog

These changes refer to the project files, and this document is updated accordingly.

• Replaced self-reset process in the top.vhd file with a separate reset_sync.vhd module
• Added demo UART loopback projects for these boards:
o Xilinx Arty A7 35T (Vivado)
o Xilinx arty S7 50 (Vivado)
o Terasic DE10-Lite + Digilent Pmod USBUART (Quartus)
1.0.2| • Changing the direction of an internal counter to make sure that the modules also work without an initial reset strobe
1.0.3| • Fixed wrong TX FIFO depth generics mapping in the uart_buffered module. It was mapped to the RX depth.

Description

This project contains three general-purpose, AXI compatible, universal asynchronous receiver-transmitter (UART) modules.
You can choose between the separate receiver (uart_rx.vhd) and transmitter (uart_tx.vhd) modules or a combined UART module (uart_buffered.vhd) with built-in input and output buffering. All three modules have built-in flow control through the use of ready/valid handshake signals. And because the signal naming scheme matches the Xilinx AXI standard, the send and recv ports will appear as bus interfaces in the Vivado Block Design editor, as  shown in the image above.
The system clock frequency and the baud rate are configurable. Data bit count is fixed to 8 (one byte), stop bits is set to 1, and parity is not used.

UART RX/TX with block RAM buffering
The uart_buffered.vhd module has built-in flow control through the AXI-style read/valid signaling scheme on the send and receive ports. Data transfer only happens when <send/recv>_tvalid and <send/recv>_tready are ‘1’ during the same rising clock edge.
Buffered bytes are stored in block RAM until they are sent by this module or read from it. The block RAM depth is configurable through generics, but the FIFO size will be that number minus one because the internal FIFO always keeps one slot open to distinguish between the full and empty states.

The listing below shows the entity for this module. UART RX
The uart_rx.vhd module contains an unbuffered UART receiver. Received data appears on the recv_tdata line and is valid when recv_tvalid is ‘1’.
The listing below shows the entity for the receiver module. UART TX
The uart_tx.vhd module contains an unbuffered UART transmitter. Data put on send_tdata is transmitted when send_tvalid is ‘1’.
The listing below shows the entity for the transmitter module.

Zip File Content

Simulating the design

There are two self-checking testbenches in the Zip file, one for the uart_buffered module and one for the generic top module used in the demo projects.
The VHDL testbench should work in any capable VHDL simulator supporting the full 2008 VHDL revision, but the provided run.do scripts only work in ModelSim/Questa.

Running the UART testbench
Open ModelSim/Questa and type in the simulator console: cd do uart_sim/run.do runtb
Running the top-level testbench
Open ModelSim/Questa and type in the simulator console: cd do loopback_demo/top_sim/run.do runtb

Implementing the demo projects

The Zip file contains demo projects for selected development boards.
If you want to try the demo on a different board, you can create a wrapper for the loopback_demo/topsrc/top.vhd module. Examine the top.vhd files and customize one to suit your board’s pin configuration and clock frequency.
The example design instantiates the uart_buffered module and echoes any bytes it receives over the UART RX pin to the TX pin.
The baud rate is set to 115200, but you can change that by altering the top wrapper VHDL files in each loopback_demo subfolder.
Lattice iCEstick
The loopback_demo/icecube2_icestick folder contains the loopback implementation for the latticesemi.com/icestick FPGA board.
To run through the implementation process, open the loopback_demo/icecube2_icestick/icecube2_project/loopback_demo_sbt.project file in the iCEcube2 | FPGA Design Software | Lattice Semiconductor design software.
After loading the project in the iCEcube2 GUI, click Tools→Run All to generate the programming bitmap file.
You can use the Lattice Diamond Programmer and Deployment Tool (latticesemi.com) tool to configure the FPGA with the generated bitmap file. When Diamond Programmer opens, click Open an existing programmer project in the welcome dialog box.
Select project file found in the Zip:
loopback_demo/icecube2_icestick/diamond_programmer_project.xcf and click OK. After the project loads, click the three dots in the File Name column, as shown above. Browse to select the bitmap file that you generated in iCEcube2:
loopback_demo/icecube2_icestick/icecube2_project/loopback_demo_Implmnt/sbt/outputs /bitmap/top_icestick_bitmap.bin Finally, with the iCEstick board plugged into a USB port on your computer, select Design→Program to program the SPI flash and  configure the FPGA.
You can now proceed to test the loopback design using a serial terminal.

Xilinx Arty A7 35T
You can find the demo implementation for the Artix-7 35T Arty FPGA evaluation kit in the loopback_demo/vivado_arty_a7_35t folder.
Open Vivado – Wikipedia and navigate to the extracted files using the Tcl console found at the bottom of the GUI interface. Type this command to enter the demo project folder:
cd /loopback_demo/vivado_arty_a7_35t/
Execute the create_vivado_proj.tcl Tcl script to regenera te the Vivado project:
source ./create_vivado_proj.tcl
Click Generate Bitstream in the sidebar to run through all the implementation steps and generate the programming bitstream file.
Finally, click Open Hardware Manager and program the FPGA through the GUI.
The bitfile should be in this folder: