ASMI Parallel II Intel FPGA IP User Guide

ASMI Parallel II Intel FPGA IP

The ASMI Parallel II Intel® FPGA IP provides access to the Intel FPGA configuration devices, which are the quad-serial configuration (EPCQ), low- voltage quad-serial configuration (EPCQ-L), and EPCQ-A serial configuration. You can use this IP to read and write data to the external flash devices for applications, such as remote system update and SEU Sensitivity Map Header File (.smh) storage.
Other than the features supported by the ASMI Parallel Intel FPGA IP, the ASMI Parallel II Intel FPGA IP additionally supports:

• Direct flash access (write/read) through the Avalon® memory-mapped interface.
• Control register for other operations through the control status register (CSR) interface in the Avalon memory-mapped interface.
• Translate the generic commands from the Avalon memory-mapped interface into device command codes.

The ASMI Parallel II Intel FPGA IP is available for all Intel FPGA device families including the Intel MAX® 10 devices which are using the GPIO mode.
The ASMI Parallel II Intel FPGA IP only supports the EPCQ, EPCQ-L, and EPCQ-A devices. If you are using third-party flash devices, you must use the Generic Serial Flash Interface Intel FPGA IP.
The ASMI Parallel II Intel FPGA IP is supported in the Intel Quartus® Prime software version 17.0 and onwards.
Related Information

• Introduction to Intel FPGA IP Cores
  • Provides general information about all Intel FPGA IP cores, including parameterizing, generating, upgrading, and simulating IP cores.
• Creating Version-Independent IP and Qsys Simulation Scripts
  • Create simulation scripts that do not require manual updates for software or IP version upgrades.
• Project Management Best Practices
  • Guidelines for efficient management and portability of your project and IP files.
• ASMI Parallel Intel FPGA IP Core User Guide
• Generic Serial Flash Interface Intel FPGA IP User Guide
  • Provides support for third-party flash devices.
• AN 720: Simulating the ASMI Block in Your Design

Release Information

IP versions are the same as the Intel Quartus Prime Design Suite software versions up to v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
The IP version (X.Y.Z) number may change from one Intel Quartus Prime software version to another. A change in:

• X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
• Y indicates the IP includes new features. Regenerate your IP to include these new features.
• Z indicates the IP includes minor changes. Regenerate your IP to include these changes.

Table 1. ASMI Parallel II Intel FPGA IP Release Information

Ports

Figure 1. Ports Block Diagram

Table 2. Ports Description

Avalon Memory-Mapped Slave Interface for CSR (avl_csr)
avl_csr_addr| 6| Input| Avalon memory-mapped interface address bus. The address bus is in word addressing.
avl_csr_read| 1| Input| Avalon memory-mapped interface read control to the CSR.
avl_csr_rddata| 32| Output| Avalon memory-mapped interface read data bus from the CSR.
avl_csr_write| 1| Input| Avalon memory-mapped interface write control to the CSR.
avl_csr_writedata| 32| Input| Avalon memory-mapped interface write data bus to CSR.
avl_csr_waitrequest| 1| Output| Avalon memory-mapped interface waitrequest control from the CSR.
avl_csr_rddatavalid| 1| Output| Avalon memory-mapped interface read data valid that indicates the CSR read data is available.
**Avalon Memory-Mapped Slave Interface for Memory Access (avl mem)**
avl_mem_write| 1| Input| Avalon memory-mapped interface write control to the memory
avl_mem_burstcount| 7| Input| Avalon memory-mapped interface burst count for the memory. The value range from 1 to 64 (maximum page size).
avl_mem_waitrequest| 1| Output| Avalon memory-mapped interface waitrequest control from the memory.
avl_mem_read| 1| Input| Avalon memory-mapped interface read control to the memory
avl_mem_addr| N| Input| Avalon memory-mapped interface address bus. The address bus is in word addressing.

The width of the address depends on the flash memory density used.

avl_mem_writedata| 32| Input| Avalon memory-mapped interface write data bus to the memory
avl_mem_readddata| 32| Output| Avalon memory-mapped interface read data bus from the memory.
avl_mem_rddata_valid| 1| Output| Avalon memory-mapped interface read data valid that indicates the memory read data is available.
avl_mem_byteenble| 4| Input| Avalon memory-mapped interface write data enable bus to memory. During bursting mode, byteenable bus will be logic high, 4’b1111.
Clock and Reset
clk| 1| Input| Input clock to clock the IP. (1)
reset_n| 1| Input| Asynchronous reset to reset the IP.(2)
Conduit Interface (3)
fqspi_dataout| 4| Bidirectional| Input or output port to feed data from the flash device.
continued…
Signal| Width| Direction| Description
---|---|---|---
qspi_dclk| 1| Output| Provides clock signal to the flash device.
qspi_scein| 1| Output| Provides the ncs signal to the flash device.

Supports Stratix® V, Arria® V, Cyclone® V, and older devices.

3| Output| Provides the ncs signal to the flash device.

Supports Intel Arria 10 and Intel Cyclone 10 GX devices.

• You can set the clock frequency to lower or equal to 50 MHz.
• Hold the signal for at least one clock cycle to reset the IP.
• Available when you enable the Disable dedicated Active Serial interface parameter.

Related Information

• Quad-Serial Configuration (EPCQ) Devices Datasheet
• EPCQ-L Serial Configuration Devices Datasheet
• EPCQ-A Serial Configuration Device Datasheet

Parameters

Table 3. Parameter Settings

EPCQ512, EPCQ-L256, EPCQ-L512, EPCQ-L1024, EPCQ4A, EPCQ16A, EPCQ32A, EPCQ64A, EPCQ128A| Specifies the EPCQ, EPCQ-L, or EPCQ-A device type you want to use.
Choose I/O mode| NORMAL STANDARD DUAL QUAD| Selects extended data width when you enable the Fast Read operation.
Disable dedicated Active Serial interface| —| Routes the ASMIBLOCK signals to the top level of your design.
Enable SPI pins interface| —| Translates the ASMIBLOCK signals to the SPI pin interface.
Enable flash simulation model| —| Uses the default EPCQ 1024 simulation model for simulation. If you are using a third-party flash device, refer to AN 720: Simulating the ASMI Block in Your Design to create a wrapper to connect the flash model with the ASMI Block.
Number of Chip Select used| 1

2(4)

3(4)

| Selects the number of chip select connected to the flash.

• Only supported in Intel Arria 10 devices, Intel Cyclone 10 GX devices, and other devices with Enable SPI pins interface enabled.

Related Information

• Quad-Serial Configuration (EPCQ) Devices Datasheet
• EPCQ-L Serial Configuration Devices Datasheet
• EPCQ-A Serial Configuration Device Datasheet
• AN 720: Simulating the ASMI Block in Your Design

Register Map

Table 4. Register Map

• Each address offset in the following table represents 1 word of memory address space.
• All registers have a default value of 0x0.

Offset| Register Name| R/W| Field Name| Bit| Width| Description
---|---|---|---|---|---|---
0| WR_ENABLE| W| WR_ENABLE| 0| 1| Write 1 to perform write enable.
1| WR_DISABLE| W| WR_DISABLE| 0| 1| Write 1 to perform write disable.
2| WR_STATUS| W| WR_STATUS| 7:0| 8| Contains the information to write to the status register.
3| RD_STATUS| R| RD_STATUS| 7:0| 8| Contains the information from read status register operation.
4| SECTOR_ERASE| W| Sector Value| 23:0

or 31:0

| 24 or

32

| Contain the sector address to be erased depending on device density.(5)
5| SUBSECTOR_ERASE| W| Subsector Value| 23:0

or 31:0

| 24 or

32

| Contains the subsector address to be erased depending on device density.(6)
6 – 7| Reserved
8| CONTROL| W/R| CHIP SELECT| 7:4| 4| Selects flash device. The default value is 0, which targets first flash device. To select second device, set the value to 1, to select the third device, set the value to 2.
Reserved
W/R| DISABLE| 0| 1| Set this to 1 to disable the SPI signals of the IP by putting all output signal to high-Z state.
continued…
Offset| Register Name| R/W| Field Name| Bit| Width| Description
---|---|---|---|---|---|---
 |  |  |  |  |  | This can be used to share bus with other devices.
9 – 12| Reserved
13| WR_NON_VOLATILE_CONF_REG| W| NVCR value| 15:0| 16| Writes value to non- volatile configuration register.
14| RD_NON_VOLATILE_CONFREG| R| NVCR value| 15:0| 16| Reads value from non- volatile configuration register
15| RD FLAG_ STATUSREG| R| RD FLAG_ STATUS_REG| 8| 8| Reads flag status register
16| CLRFLAG STATUS REG| W| CLRFLAG STATUS REG| 8| 8| Clears flag status register
17| BULK_ERASE| W| BULK_ERASE| 0| 1| Write 1 to erase entire chip (for single- die device).(7)
18| DIE_ERASE| W| DIE_ERASE| 0| 1| Write 1 to erase entire die (for stack-die device).(7)
19| 4BYTES_ADDR_EN| W| 4BYTES_ADDR_EN| 0| 1| Write 1 to enter 4 bytes address mode
20| 4BYTES_ADDR_EX| W| 4BYTES_ADDR_EX| 0| 1| Write 1 to exit 4 bytes address mode
21| SECTOR_PROTECT| W| Sector protect value| 7:0| 8| Value to write to status register to protect a sector. (8)
22| RD_MEMORY_CAPACITY_ID| R| Memory capacity value| 7:0| 8| Contains the information of memory capacity ID.
23 –

32

| Reserved

You only need to specify any address within the sector and the IP will erase that particular sector.
You only need to specify any address within the subsector and the IP will erase that particular subsector.

Related Information

• Quad-Serial Configuration (EPCQ) Devices Datasheet
• EPCQ-L Serial Configuration Devices Datasheet
• EPCQ-A Serial Configuration Device Datasheet
• Avalon Interface Specifications

Operations

The ASMI Parallel II Intel FPGA IP interfaces are Avalon memory-mapped interface compliant. For more details, refer to the Avalon specifications.

• You only need to specify any address within the die and the IP will erase that particular die.
• For EPCQ and EPCQ-L devices, the block protect bit are bit [2:4] and [6] and the top/bottom (TB) bit is bit 5 of the status register. For EPCQ-A devices. the block protect bit are bit [2:4] and the TB bit is bit 5 of the status register.

Related Information

• Avalon Interface Specifications

Control Status Register Operations

You can perform a read or write to a specific address offset using the Control Status Register (CSR).
To execute the read or write operation for the control status register, follow these steps:

1. Assert the avl_csr_write or avl_csr_read signal while the
   avl_csr_waitrequest signal is low (if the waitrequest signal is high, the avl_csr_write or avl_csr_read signal must to be kept high until the waitrequest signal goes low).

2. At the same time, set the address value on the avl_csr_address bus. If it is a write operation, set the value data on the avl_csr_writedata bus together with the address.

3. If it is a read transaction, wait until the avl_csr_readdatavalid signal is asserted high to retrieve the read data.

• For operations that require write value to flash, you must perform the write enable operation first.
• You must read the flag status register every time you issue a write or erase command.
• If multiple flash devices are used, you must write to the chip select register to select the correct chip select before performing any operation to the specific flash device.

Figure 2. Read Memory Capacity Register Waveform Example

Figure 3. Write Enable Register Waveform Example

Memory Operations

The ASMI Parallel II Intel FPGA IP memory interface supports bursting and direct flash memory access. During the direct flash memory access, the IP performs the following steps to allow you to perform any direct read or write operation:

• Write enable for the write operation
• Check flag status register to make sure the operation has been completed at the flash
• Release the waitrequest signal when the operation is completed

Memory operations are similar to the Avalon memory-mapped interface operations. You must set the correct value at the address bus, write data if it is a write transaction, drive the burst count value to 1 for single transaction or your desired burst count value, and trigger the write or read signal.

Figure 4. 8-Word Write Burst Waveform Example

Figure 5. 8-Word Reading Burst Waveform Example

Figure 6. 1-Byte Write byteenable = 4’b0001 Waveform Example

ASMI Parallel II Intel FPGA IP Use Case Examples

The use case examples use the ASMI Parallel II IP and JTAG-to-Avalon Master to perform flash access operations, such as read silicon ID, read memory, write memory, sector erase, sector protect, clear flag status register, and write nvcr.
To run the examples, you must configure the FPGA. Follow these steps:

1. Configure the FPGA based on Platform Designer system as shown in the following figure.
   Figure 7. Platform Designer System Showing the ASMI Parallel II IP and JTAG-to-Avalon Master

2. Save the following TCL script in the same directory as your project. Name the script as epcq128_access.tcl for example.

3. Launch system console. In the console, source the script by using “source epcq128_access.tcl”.

Example 1: Read the Silicon ID of the Configuration Devices

Example 2: Read and Write One Word of Data at Address H’40000000

Example 3: Erase Sector 64

Example 4: Perform Sector Protect at Sectors (0 to 127)

Example 5: Read and Clear Flag Status Register

Example 6: Read and Write nvcr

ASMI Parallel II Intel FPGA IP User Guide Archives

IP versions are the same as the Intel Quartus Prime Design Suite software versions up to v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
If an IP core version is not listed, the user guide for the previous IP core version applies.

Guide](https://www.intel.com/content/dam/altera- www/global/en_US/pdfs/literature/ug/archives/ug-asmi2-17-0.pdf)

Document Revision History for the ASMI Parallel II Intel FPGA IP User

Guide

Document Version| Intel Quartus Prime Version| IP Version| Changes
---|---|---|---
2020.07.29| 18.0| 18.0| •    Updated the document title to ASMI Parallel II Intel FPGA IP User Guide.

•    Updated Table 2: Parameter Settings in section

Parameters.

2018.09.24| 18.0| 18.0| •    Added information on the applications and support for the ASMI Parallel II Intel FPGA IP core.

•    Added a note to refer to the Generic Serial Flash Interface Intel FPGA IP Core User Guide.

•    Added the ASMI Parallel II Intel FPGA IP Core Use Case Examples section.

2018.05.07| 18.0| 18.0| •    Renamed Altera ASMI Parallel II IP core to ASMI Parallel II Intel FPGA IP core per Intel rebranding.

•    Added support for EPCQ-A devices.

•    Added a note to the clk signal in the Ports Description table.

•    Updated the description for the qspi_scein signal in the Ports Description table.

•    Added a note to the SECTOR_PROTECT register in the Register Map table.

•    Updated the bit and width for SECTOR_ERASE and SUBSECTOR_ERASE registers in the Register Map table.

•    Updated the bit and width for SECTOR_PROTECT

register in the Register Map table.

continued…
Document Version| Intel Quartus Prime Version| IP Version| Changes
---|---|---|---
 |  |  | •    Updated the description for the CHIP SELECT option of the CONTROL register in the Register Map table.

•    Updated the footnotes for the SECTOR_ERASE, SUBSECTOR_ERASE, BULK_ERASE, and DIE_ERASE registers in the Register Map table.

•    Updated the description for the vl_mem_addr

signal in the Ports Description table.

•    Minor editorial edits.

Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.

References

• 1. Quad-Serial Configuration (EPCQ) Devices Datasheet
• 1. Simulating the ASMI Block in Your Design
• 1. ASMI Parallel Intel® FPGA IP Core User Guide
• 1. EPCQ-A Serial Configuration Device Datasheet
• EPCQ-L Serial Configuration Devices Datasheet

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