intel F-Tile CPRI PHY FPGA IP Design Example User Guide

: June 9, 2024
: Intel

intel F-Tile CPRI PHY FPGA IP Design Example

intel F-Tile CPRI PHY FPGA IP Design Example
product

Quick Start Guide

The F-Tile CPRI PHY Intel® FPGA IP core provides a simulation testbench and hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Intel also provides a compilation-only example project that you can use to quickly estimate IP core area and timing.
The F-Tile CPRI PHY Intel FPGA IP core provides the capability of generating design examples for all supported combinations of number of CPRI channels and CPRI line bit rates. The testbench and design example support numerous parameter combinations of the F-Tile CPRI PHY Intel FPGA IP core.

Figure 1. Development Steps for the Design Example

Related Information

F-Tile CPRI PHY Intel FPGA IP User Guide
- For detailed information on F-tile CPRI PHY IP.
F-Tile CPRI PHY Intel FPGA IP Release Notes
- The IP Release Notes list IP changes in a particular release.

Hardware and Software Requirements

To test the example design, use the following hardware and software:

Intel Quartus® Prime Pro Edition software
System console
Supported Simulators:
- Synopsys VCS
- Synopsys VCS MX
- Siemens EDA ModelSim SE or Questa*— Questa-Intel FPGA Edition

Generating the Design

Figure 2. Procedure

intel F-Tile CPRI PHY FPGA IP Design Example fig 2 Figure 3. Example Design Tab in IP Parameter Editor

intel F-Tile CPRI PHY FPGA IP Design Example fig 3

To create an Intel Quartus Prime Pro Edition project:

In the Intel Quartus Prime Pro Edition, click File ➤ New Project Wizard to create a new Quartus Prime project, or File ➤ Open Project to open an existing Intel Quartus Prime project. The wizard prompts you to specify a device.
Specify the device family Agilex (I-series) and select a device that meets all of these requirements:
- Transceiver tile is F-tile
- Transceiver speed grade is -1 or -2
- Core speed grade is -1 or -2 or -3
Click Finish.

Follow these steps to generate the F-Tile CPRI PHY Intel FPGA IP hardware design example and testbench:

In the IP Catalog, locate and select F-Tile CPRI PHY Intel FPGA IP. The New IP Variation window appears.
Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named .ip.
Click OK. The parameter editor appears.
On the IP tab, specify the parameters for your IP core variation.
On the Example Design tab, under Example Design Files, select the Simulation option to generate the testbench and the compilation-only project. Select the Synthesis option to generate the hardware design example. You must select at least one of the Simulation and Synthesis options to generate the design example.
On the Example Design tab, under Generated HDL Format, select Verilog HDL or VHDL. If you select VHDL, you must simulate the testbench with a mixed-language simulator. The device under test in the ex_ directory is a VHDL model, but the main testbench file is a System Verilog file.
Click the Generate Example Design button. The Select Example Design Directory window appears.
If you want to modify the design example directory path or name from the defaults displayed (cpriphy_ftile_0_example_design), browse to the new path and type the new design example directory name ().

Directory Structure

The F-Tile CPRI PHY Intel FPGA IP core design example file directories contain the following generated files for the design example.

Figure 4. Directory Structure of the Generated Example Design

intel F-Tile CPRI PHY FPGA IP Design Example fig 4

Table 1. Testbench File Descriptions

File Names	Description

Key Testbench and Simulation Files

/ example_testbench/basic_avl_tb_top.sv| Top-level testbench file. The testbench instantiates the DUT wrapper and runs Verilog HDL tasks to generate and accept packets. / example_testbench/ cpriphy_ftile_wrapper.sv| DUT wrapper that instantiates DUT and other testbench components. Testbench Scripts(1) / example_testbench/run_vsim.do| The Siemens EDA ModelSim SE or Questa or Questa-Intel FPGA Edition script to run the testbench. / example_testbench/run_vcs.sh| The Synopsys VCS script to run the testbench. / example_testbench/run_vcsmx.sh| The Synopsys VCS MX script (combined Verilog HDL and SystemVerilog with VHDL) to run the testbench.

Ignore any other simulator script in the

/example_testbench/ folder.

Table 2. Hardware Design Example File Descriptions

File Names	Descriptions
/hardware_test_design/ cpriphy_ftile_hw.qpf	Intel Quartus

Prime project file.

/hardware_test_design/ cpriphy_ftile_hw.qsf| Intel Quartus Prime project setting file. /hardware_test_design/ cpriphy_ftile_hw.sdc| Synopsys Design Constraints files. You can copy and modify these files for your own Intel Agilex™ design. /hardware_test_design/ cpriphy_ftile_hw.v| Top-level Verilog HDL design example file. /hardware_test_design/ cpriphy_ftile_wrapper.sv| DUT wrapper that instantiates DUT and other testbench components. /hardware_test_design/ hwtest_sl/main_script.tcl| Main file for accessing System Console.

Simulating the Design Example Testbench

Figure 5. Procedure

intel F-Tile CPRI PHY FPGA IP Design Example fig 5

Follow these steps to simulate the testbench:

At the command prompt, change to the testbench simulation directory /example_testbench. cd /example_testbench
Run quartus_tlg on the generated project file: quartus_tlg cpriphy_ftile_hw
Run ip-setup-simulation: ip-setup-simulation –output-directory=./sim_script –use-relative-paths –quartus project=cpriphy_ftile_hw.qpf
Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
Analyze the results. The successful testbench received five hyperframes, and displays “PASSED”.

*Table 3. Steps to Simulate the Testbench in Synopsys VCS Simulator**

Simulator	Instructions
VCS	In the command line, type:
sh run_vcs.sh

continued…
Simulator| Instructions
---|---
VCS MX| In the command line, type:
sh run_vcsmx.sh|
ModelSim SE or Questa or Questa-Intel FPGA Edition| In the command line, type:
vsim -do run_vsim.do|
If you prefer to simulate without bringing up the GUI, type:
vsim -c -do run_vsim.do|

The following sample output illustrates a successful simulation test run for 24.33024 Gbps with 4 CPRI channels:

intel F-Tile CPRI PHY FPGA IP Design Example fig 9

Compiling the Compilation-Only Project

To compile the compilation-only example project, follow these steps:

Ensure compilation design example generation is complete.
In the Intel Quartus Prime Pro Edition software, open the Intel Quartus Prime Pro Edition project /compilation_test_design/cpriphy_ftile.qpf.
On the Processing menu, click Start Compilation.
After successful compilation, reports for timing and for resource utilization are available in your Intel Quartus Prime Pro Edition session.

Related Information
Block-Based Design Flows

Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Intel Agilex device, follow these steps:

Ensure hardware design example generation is complete.
In the Intel Quartus Prime Pro Edition software, open the Intel Quartus Prime project /hardware_test_design/ cpriphy_ftile_hw.qpf.
Edit the .qsf file to assign pins based on your hardware.
On the Processing menu, click Start Compilation.
After successful compilation, a .sof file is available in /hardware_test_design/output_files directory.

Follow these steps to program the hardware design example on the Intel Agilex device:

Connect Intel Agilex I-series Transceiver Signal Integrity Development Kit to the host computer.
Note: The development kit is preprogrammed with the correct clock frequencies by default. You do not need to use the Clock Control application to set the frequencies.
On the Tools menu, click Programmer.
In the Programmer, click Hardware Setup.
Select a programming device.
Ensure that Mode is set to JTAG.
Select the Intel Agilex device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
In the row with your .sof, check the box for the .sof.
Check the box in the Program/Configure column.
Click Start.

Related Information

Block-Based Design Flows
Programming Intel FPGA Devices
Analyzing and Debugging Designs with System Console

Testing the Hardware Design Example

After you compile the F-Tile CPRI PHY Intel FPGA IP core design example and configure it on your Intel Agilex device, you can use the System Console to program the IP core and its PHY IP core registers.
To turn on the System Console and test the hardware design example, follow these steps:

After the hardware design example is configured on the Intel Agilex device, in the Intel Quartus Prime Pro Edition software, on the Tools menu, click System Debugging Tools ➤ System Console.
In the Tcl Console pane, type cd hwtest to change directory to /hardware_test_design/hwtest_sl.
Type source main_script.tcl to open a connection to the JTAG master and start the test.

Design Example Description

The design example demonstrates the basic functionality of the F-Tile CPRI PHY Intel FPGA IP core. You can generate the design from the Example Design tab in the F-Tile CPRI PHY Intel FPGA IP parameter editor.
To generate the design example, you must first set the parameter values for the IP core variation you intend to generate in your end product. You can choose to generate the design example with or without the RS-FEC feature. The RS-FEC feature is available with 10.1376, 12.1651 and 24.33024 Gbps CPRI line bit rates.
Table 4. F-Tile CPRI PHY Intel FPGA IP Core Feature Matrix

CPRI Line Bit Rate (Gbps)| RS-FEC Support| Reference Clock (MHz)| Deterministic Latency Support
---|---|---|---
1.2288| No| 153.6| Yes
2.4576| No| 153.6| Yes
3.072| No| 153.6| Yes
4.9152| No| 153.6| Yes
6.144| No| 153.6| Yes
9.8304| No| 153.6| Yes
10.1376| With and Without| 184.32| Yes
12.1651| With and Without| 184.32| Yes
24.33024| With and Without| 184.32| Yes

Features

Generate the design example with RS-FEC feature
Basic packet checking capabilities including round trip latency count

Simulation Design Example

The F-Tile CPRI PHY Intel FPGA IP design example generates a simulation testbench and simulation files that instantiates the F-Tile CPRI PHY Intel FPGA IP core when you select the Simulation option.

Figure 6. Block Diagram for 10.1316, 12.1651, and 24.33024 Gbps (with and without RS-FEC) Line Rates

intel F-Tile CPRI PHY FPGA IP Design Example fig 6 Figure 7. Block Diagram for 1.228, 2.4576, 3.072, 4.9152, 6.144, and 9.8304 Gbps Line Rate

intel F-Tile CPRI PHY FPGA IP Design Example fig 7

In this design example, the simulation testbench provides basic functionality such as startup and wait for lock, transmit and receive packets.
The successful test run displays output confirming the following behavior:

The client logic resets the IP core.
The client logic waits for the RX datapath alignment.
The client logic transmits hyperframes on the TX MII interface and waits for five hyperframes to be received on RX MII interface. Hyperframes are transmitted and received on MII interface according to the CPRI v7.0 specifications.
Note: The CPRI designs that target 1.2, 2.4, 3, 4.9, 6.1, and 9.8 Gbps line rate use 8b/10b interface and the designs that target 10.1, 12.1 and 24.3 Gbps (with and without RS-FEC) use MII interface. This design example includes a round trip counter to count the round trip latency from TX to RX.
The client logic reads the round trip latency value and checks for the content and correctness of the hyperframes data on the RX MII side once the counter completes the round trip latency count.

Related Information

CPRI Specifications

Hardware Design Example

Figure 8. Hardware Design Example Block Diagram

intel F-Tile CPRI PHY FPGA IP Design Example fig 8

Note

The CPRI designs with 2.4/4.9/9.8 Gbps CPRI line rates use 8b/10b interface and all other CPRI line rates designs use MII interface.
The CPRI designs with 2.4/4.9/9.8 Gbps CPRI line rates need 153.6 MHz transceiver reference clock and all other CPRI line rates need 184.32 MHz.

The F-Tile CPRI PHY Intel FPGA IP core hardware design example includes the following components:

F-Tile CPRI PHY Intel FPGA IP core.
Packet client logic block that generates and receives traffic.
Round trip counter.
IOPLL to generate sampling clock for deterministic latency logic inside the IP, and round trip counter component at testbench.
System PLL to generate system clocks for the IP.
Avalon®-MM address decoder to decode reconfiguration address space for CPRI, Transceiver, and Ethernet modules during reconfiguration accesses.
Sources and probes for asserting resets and monitoring the clocks and a few status bits.
JTAG controller that communicates with the System Console. You communicate with the client logic through System Console.

Interface Signals

Table 5. Design Example Interface Signals

Signal	Direction	Description
ref_clk100MHz	Input	Input clock for CSR access on all the reconfiguration

interfaces. Drive at 100 MHz.
i_clk_ref[0]| Input| Reference clock for System PLL. Drive at 156.25 MHz.
i_clk_ref[1]| Input| Transceiver reference clock. Drive at

• 153.6 MHz for CPRI line rate 1.2, 2.4, 3, 4.9, 6.1, and 9.8 Gbps.

• 184.32 MHz for CPRI line rates 10.1,12.1, and 24.3 Gbps with and without RS-FEC.

i_rx_serial[n]| Input| Transceiver PHY input serial data.
o_tx_serial[n]| Output| Transceiver PHY output serial data.

Design Example Registers

Table 6. Design Example Registers

Channel Number	Base Address (Byte Address)	Register Type

0

| 0x00000000| CPRI PHY Reconfiguration registers for Channel 0
0x00100000| Ethernet Reconfiguration registers for Channel 0
0x00200000| Transceiver Reconfiguration registers for Channel 0

1(2)

| 0x01000000| CPRI PHY Reconfiguration registers for Channel 1
0x01100000| Ethernet Reconfiguration registers for Channel 1
0x01200000| Transceiver Reconfiguration registers for Channel 1

2(2)

| 0x02000000| CPRI PHY Reconfiguration registers for Channel 2
0x02100000| Ethernet Reconfiguration registers for Channel 2
0x02200000| Transceiver Reconfiguration registers for Channel 2
continued…
Channel Number| Base Address (Byte Address)| Register Type
---|---|---

3(2)

| 0x03000000| CPRI PHY Reconfiguration registers for Channel 3
0x03100000| Ethernet Reconfiguration registers for Channel 3
0x03200000| Transceiver Reconfiguration registers for Channel 3

These registers are reserved if the channel is not used.

F-Tile CPRI PHY Intel FPGA IP Design Example User Guide Archives

If an IP core version is not listed, the user guide for the previous IP core version applies.

Intel Quartus Prime Version	IP Core Version	User Guide
21.2	2.0.0	[F-Tile CPRI PHY Intel FPGA IP Design Example User

Guide](https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug20328-21-2-2-0-0.pdf)

Document Revision History for F-Tile CPRI PHY Intel FPGA IP Design

Example User Guide

Document Version| Intel Quartus Prime Version| IP Version| Changes
---|---|---|---
2021.10.04| 21.3| 3.0.0|

Added support for new simulators in section: Hardware and Software Requirements.
Updated steps in section: Simulating the Design Example Testbench.
Updated the following sections with new line rate information:
- Design Example Description
- Simulation Design Example
- Interface Signals
Updated the address in section: Design Example Registers.

2021.06.21| 21.2| 2.0.0| Initial release.

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