intel AN 775 Generating Initial I/O Timing Data User Guide

: June 3, 2024
: Intel

Table of Contents

AN 775: Generating Initial I/O Timing Data for Intel FPGAs
Read User Manual Online (PDF format)
Download This Manual (PDF format)

intel AN 775 Generating Initial I/O Timing Data

intel Logo

AN 775: Generating Initial I/O Timing Data for Intel FPGAs

You can generate initial I/O timing data for Intel FPGA devices using the Intel® Quartus® Prime software GUI or Tcl commands. Initial I/O timing data is useful for early pin planning and PCB design. You can generate initial timing data for the following relevant timing parameters to adjust the design timing budget when considering I/O standards and pin placement.

Table 1. I/O Timing Parameters

Timing Parameter

|

Description

---|---
Input setup time (tSU)
Input hold time (tH)| I/O Timing Parameters |

tSU =
input pin to input register data delay
+ input register micro setup time
- input pin to input register clock delay

tH =
- input pin to input register data delay
+ input register micro hold time
+ input pin to input register clock delay

Clock to output delay (tCO)| I/O Timing
Parameters

|

tCO =
+ clock pad to output register delay
+ output register clock-to-output delay
+ output register to output pin delay

Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.

Generating initial I/O timing information includes the following steps:

Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device on page 4
Step 2: Define I/O Standard and Pin Locations on page 5
Step 3: Specify Device Operating Conditions on page 6
Step 4: View I/O Timing in Datasheet Report on page 6

I/O Timing Data Generation Flow

Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device

Follow these steps to define and synthesize the minimum flip-flop logic to generate initial I/O timing data:

Create a new project in Intel Quartus Prime Pro Edition software version 19.3.
Click Assignments ➤ Device, specify your target device Family and a Target device. For example, select the AGFA014R24 Intel Agilex™ FPGA.
Click File ➤ New and create a Block Diagram/Schematic File.
To add components to the schematic, click the Symbol Tool button.
Under Name, type DFF, and then click OK. Click in the Block Editor to insert the DFF symbol.
Repeat 4 on page 4 through 5 on page 5 to add an Input_data input pin, Clock input pin, and Output_data output pin.
To connect the pins to the DFF, click the Orthogonal Node Tool button, and then draw wire lines between the pin and DFF symbol.
To synthesize the DFF, click Processing ➤ Start ➤ Start Analysis & Synthesis. Synthesis generates the minimum design netlist required to obtain I/O timing Data.

Step 2: Define I/O Standard and Pin Locations

The specific pin locations and I/O standard you assign to the device pins impacts the timing parameter values. Follow these steps to assign the pin I/O standard and location constraints:

Click Assignments ➤ Pin Planner.
Assign pin location and I/O standard constraints according to your design
specifications. Enter the Node Name, Direction, Location, and I/O Standard values for the pins in the design in the All Pins spreadsheet. Alternatively, drag node names into the Pin Planner package view.

Pin Locations and I/O Standards Assignments in Pin
Planner

To compile the design, click Processing ➤ Start Compilation. The Compiler generates I/O timing information during full compilation.

Related Information

I/O Standards Definition
Managing Device I/O Pins

Step 3: Specify Device Operating Conditions

Follow these steps to update the timing netlist and set operating conditions for timing analysis following full compilation:

Click Tools ➤ Timing Analyzer.
In the Task pane, double-click Update Timing Netlist. The timing netlist updates with full compilation timing information that accounts for the pin constraints you make.
Under Set Operating Conditions, select one of the available timing models, such as Slow vid3 100C Model or Fast vid3 100C Model.

Set Operating Conditions in the Timing Analyzer

Step 4: View I/O Timing in Datasheet Report

Generate the Datasheet Report in the Timing Analyzer to view the timing parameter values.

In the Timing Analyzer, click Reports ➤ Datasheet ➤ Report Datasheet.
Click OK.

Datasheet Report in Timing Analyzer
The Setup Times, Hold Times, and Clock to Output Times reports appear under the Datasheet Report folder in the Report pane.

Click each report to view the Rise and Fall parameter values.
For a conservative timing approach, specify the maximum absolute value

Example 1. Determining I/O Timing Parameters from the Datasheet Report

In the following example Setup Times report, the fall time is greater than the rise time, therefore tSU=tfall.

In the following example Hold Times report, the absolute value of the fall time is greater than the absolute value of the rise time, therefore tH=tfall.

In the following example Clock to Output Times report, the absolute value of the fall time is greater than the absolute value of the rise time, therefore tCO=tfall.

Clock to Output Times Report

Related Information

Scripted I/O Timing Data Generation

You can use a Tcl script to generate I/O timing information with or without using the Intel Quartus Prime software user interface. The scripted approach generates textbased I/O timing parameter data for supported I/O standards.

Note : The scripted method is available only for Linux* platforms.
Follow these steps to generate I/O timing information reflecting multiple I/O standards for Intel Agilex, Intel Stratix® 10, and Intel Arria® 10 devices:

Download the appropriate Intel Quartus Prime project archive file for your target device family:
• Intel Agilex devices— https://www.intel.com/content/dam/www/programmable/us/en/others/literature/an/io_timing_agilex_latest.qar
• Intel Stratix 10 devices— https://www.intel.com/content/dam/www/programmable/us/en/others/literature/an/io_timing_stratix10.qar
• Intel Arria 10 devices— https://www.intel.com/content/dam/www/programmable/us/en/others/literature/an/io_timing_arria10.qar
To restore the .qar project archive, launch the Intel Quartus Prime Pro Edition software and click Project ➤ Restore Archived Project. Alternatively, run the following command line equivalent without launching the GUI:

quartus_sh --restore

The io_timing__restored directory now contains the qdb subfolder and various files.

To run the script with the Intel Quartus Prime Timing Analyzer, run the following command:

quartus_sta –t .tcl

Wait for completion. The script execution may require 8 hours or more because each change on I/O standard or pin location requires design recompilation.