ANALOG DEVICES EVAL-LT8418-BZ 100V Half-Bridge GaN Driver with Smart Integrated Bootstrap Switch User Guide

ANALOG DEVICES EVAL-LT8418-BZ 100V Half-Bridge GaN Driver with Smart

Integrated Bootstrap Switch User Guide

EVAL-LT8418-BZ

General Description

The EVAL-LT8418-BZ evaluation circuit features the LT8418 driving two 100V enhanced Gallium Nitride (eGaN) FETs in a half-bridge configuration. The circuit is optimized as a buck converter, but it can be used as a boost converter or other converter topologies consisting of a half-bridge. The evaluation circuit can deliver up to 10A with good thermal management.

An external single or two PWM signals are required to drive the board, depending on the configuration. In the single-input setup, the dead time circuitry on the board is utilized to generate the complement signal and set the dead time. The dead time circuitry is bypassed in the dual-input setup.

The LT8418 driver has powerful 0.2Ω pull-down and 0.6Ω pull-up drivers driving two 100V GaN FETs. It also integrates a smart integrated bootstrap switch to generate a balanced bootstrap voltage from VCC with a minimum dropout voltage. The LT8418 provides split gate drivers to adjust the turn-on and turn-off slew rates of GaN FETs to suppress ringing and optimize EMI performance.

Design files for this circuit board are available.

Performance Summary (TA = 25C)

1. Maximum input voltage depends on inductive loading. Maximum switch node ringing must be kept under 100V for EPC2204.
2. Maximum output current depends on EPC2204 FET temperature, affected by switching frequency, input voltage, output voltage, and thermal management. Make sure to monitor the die temperature when setting the output current.
3. At high switching frequencies, switching loss is dominant. Input voltage and output current should be reduced to prevent overheating of the GaN FETs.

Quick Start Procedure

The EVAL-LT8418-BZ evaluation circuit is an power stage used to evaluate the performance of the LT8418. See Figure 1 for proper measurement equipment setup and use the following procedure:

1. With power off, connect the input power supply to the board through the VIN and GND terminals. Connect the auxiliarypower supply to the AUX INPUT and GND terminals. Connect the load to the VOUT and GND terminals. Connect thefunction generator output to the INT and GND pins of header J1.
2. Turn on the auxiliary power supply at 6V.
3. Set the function generator to output a 5V, 1MHz, 50% duty cycle, high-Z output pulse waveform.
4. Turn on the input power supply at 0V, 7A limit. Increase the voltage slowly to 48V.
5. Check for the proper output voltage, which should be 24V (±5%).
6. Once the proper output voltage is established, adjust the input voltage and load current within the operating range,and observe the gate signals, switch node voltage, voltage ripple, efficiency, and other parameters.

NOTE: When probing the gate signals or switch node, it is recommended to use the ground spring to avoid parasitic inductance in the long ground lead. Measure the input or output voltage ripple by touching the probe tip directly across the VIN (J2) and GND (J3), or VOUT (J4) and GND (J5) terminals.

Figure 1. EVAL-LT8418-BZ Board Connections in Single-PWM-Input Control Mode

Output Voltage and Power

The EVAL-LT8418-BZ can be configured as either a buck or a boost converter, or other converter topologies consisting of a half-bridge with maximum input and output voltages of 80V. However, the converter is optimally designed to convert 48VIN to 24VOUT at 1MHZ, delivering up to 10A with a heat sink or forced airflow. At full load with forced airflow, although the board can deliver 240W, the top FET heats up significantly. Therefore, a heat sink is recommended if this operating condition is expected over an extended period. Please see the “thermal considerations” section for more details on using a heat sink.

The conversion ratio can be adjusted by changing the duty cycle of the PWM input signal(s), while the switching frequency is set by the PWM input signal frequency. To optimize the converter efficiency at a different power specification, passive power components inductors and input/output capacitors should be resized appropriately. The dead times must also be adjusted to minimize the loss during the dead time. Figure 3 and Figure 4 show the converter efficiency versus the load current at different operating conditions.

LDO Setting

An LDO (U3) is used to supply power to the LT8418 and dead time circuitry. The output voltage VCC of the LDO is set to 5V in the default configuration, but it can be adjusted by changing R2 and R4 values. The input power of U3 comes from either a default auxiliary power supply, AUX INPUT, ranging from 5.5V to 80V, or directly from the board’s input power supply, which can be selected by changing the position of jumper JP1.

Control Mode

The EVAL-LT8418-BZ circuit is an open-loop half-bridge converter without a feedback network and control loop. Hence, the board requires two complementary PWM signals to drive the INT and INB pins of the LT8418. These signals come from either one (in single-PWM-input mode) or two (in dual-PWM-input mode) external PWM signals provided by a function generator or microcontroller.

The single-PWM-input mode is the default control scheme of this evaluation board. In this mode, only a single PWM output of the function generator is connected to header J1, as shown in Figure 1. The positive terminal is tied to the leftmost pin (labeled INT), while the negative terminal is tied to the middle pin (labeled GND).

Alternatively, two separate PWM signals can be applied to header J1 to control INT and INB pins independently in the dual-PWM-input mode. To enable this control mode, some component-level modifications are required to bypass the RC filters. Specifically, R5 must be removed and R7, R3, and R6 must be shorted with 0Ω resistors. The positive sides of INT and INB inputs are applied at the leftmost pin (labeled INT) and rightmost pin (labeled INB) of header J1, respectively. As the dead time circuitry no longer generates dead times between INT and INB input signals, careful control must be taken in this control mode to prevent a shoot-through incident. Table 1 lists the circuit configurations of two control modes.

Table 1. Circuit Configurations For Control Modes

1. Default configuration
2. Resistance value can be changed to adjust the dead time

Dead Time

In the single-PWM-input control mode, the dead times of gate signals are set by the dead-time circuitry consisting of two inverters and RC filters. The input PWM signal is first inverted and split into two complementary signals by the Schmitt-trigger inverter U2. The two signals are then delayed by the RC filters, setting the dead times before being inverted again by another inverter U4. These two resulting signals are applied to the INT and INB pins driving the LT8418. The default dead times on the board are optimized for 48VIN, 24VOUT, 1MHz fSW, and 10A IOUT operating conditions. However, the dead times can be adjusted by changing R3 and R6 values to evaluate the impact of dead time on efficiency. When changing the dead times, careful design must be taken to avoid a shoot-through condition. Figure 2 shows the relationship between the resistor values and dead times between INT and INB signals.

Figure 2. Dead Times vs. Resistor Values

Thermal Considerations

At high switching frequencies and high output power, care must be taken to prevent overheating on the GaN FETs. For better thermal management, the EVAL- LT8418-BZ is equipped with four mechanical spacers that can be used to attach a heat sink (527-45AB) to the bottom layer. Since all the high-profile components are placed on the top layer, the heat sink is easily placed on the bottom layer against the surface of GaN FETs and the LT8418. A thermal pad and a thermal spreader (4051100100017) should be inserted under the heat sink to ensure good contact, improving thermal dissipation.

Measurement Considerations

A high-speed differential probe such as the IsoVu probe from Tektronix is recommended for measuring the high-side gate voltage at header TP10. It has low parasitic elements, suitable for measuring high-frequency waveforms. Low parasitic capacitance passive probes with ground springs are recommended for measuring voltage at other nodes. The surface-mount sockets (TP1-TP7) are equipped on the top layer for easy probing.

Performance

Bill of Materials

Schematic

Figure 17. EVAL-LT8418-BZ Schematic

ASSUMED BY ANALOG DEVICES FOR ITS USE, NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES THAT MAY RESULT FROM ITS USE. SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. NO LICENCE, EITHER EXPRESSED OR IMPLIED, IS GRANTED UNDER ANY ADI PATENT RIGHT, COPYRIGHT, MASK WORK RIGHT, OR ANY OTHER ADI INTELLECTUAL PROPERTY RIGHT RELATING TO ANY COMBINATION, MACHINE, OR PROCESS WHICH ADI PRODUCTS ALL INFORMATION CONTAINED HEREIN IS PROVIDED “AS IS” WITHOUT REPRESENTATION OR WARRANTY. NO RESPONSIBILITY IS OR SERVICES ARE USED. TRADEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS.
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References

• Mixed-signal and digital signal processing ICs | Analog Devices
• Document Feedback Form | Analog Devices
• Mixed-signal and digital signal processing ICs | Analog Devices

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