LINEAR TECHNOLOGY LT3045EDD-1 Paralleled Ultralow Noise Ultrahigh PSRR LDO Regulator Instruction Manual
- June 13, 2024
- LINEAR TECHNOLOGY
Table of Contents
LINEAR TECHNOLOGY LT3045EDD-1 Paralleled Ultralow Noise Ultrahigh PSRR
LDO Regulator
Product Information
The LT3045EDD-1 is a 20V, 2A, Paralleled Ultralow Noise, Ultrahigh PSRR LDO Regulator. It features built-in protection including reverse battery protection, reverse current protection, internal current limit with foldback, and thermal limit with hysteresis. The input voltage range is 3.8V to 20V and the output voltage is 3.19V to 3.39V. The LT3045EDD-1 is designed for high performance and low noise applications.
For more information and design files, visit the Analog Devices website at http://www.analog.com/DC2637A.
Product Usage Instructions
To set up the LT3045EDD-1 for evaluation, follow these steps:
- Connect the load between the VOUT and GND terminals.
- With the power off, connect the input power supply to the VIN and GND terminals.
- Make sure the shunt of JP1 is at the ON option.
- Vary VIN from 3.8V to 20V and adjust the load current up to 2A.
- Ensure that the power dissipation is below the thermal limit.
Refer to Application Notes AN70 and AN159 for measuring output noise and PSRR.
For optimal performance, follow the recommended PCB layout for input trace and output capacitors. Refer to Figure 2, Figure 3, Figure 4, and Figure 5 in the user manual for the recommended PCB layouts.
Refer to the parts list in the user manual for the required circuit components and their corresponding manufacturer/part numbers.
DESCRIPTION
Demo circuit 2637A features four LT®3045EDD-1s in par- allel, generating an ultralow noise, ultrahigh power supply rejection ratio (PSRR) low dropout (LDO) regulator with programmable current limit. DC2637A operates over an input range of 3.8V to 20V, and is capable of delivering up to 2A output current by paralleling four LT3045EDD-1s with only 20mΩ ballast resistors.
The VIOC tracking function of the LT3045EDD-1 controls an upstream switching converter to maintain a constant voltage across the regulator and hence minimize power dissipation. In the parallel configuration, connect the VIOC pin of only one IC to the switching converter, while the VIOC pins of the other ICs are left floating. The power good feedback (PGFB) pin is used to set a programmable power good threshold, and also activates the fast start-up circuitry. The PGFB is set on only one IC when they are paralleled. LT3045-1 also offers programmable current limit functionality by connecting a resistor from ILIM to GND on each device. Current monitoring is also achieved by sensing the ILIM pin voltage. Built-in protection includes reverse battery protection, reverse current protection, internal current limit with fold- back, and thermal limit with hysteresis.
The LT3045-1 data sheet gives a complete descrip- tion of the device, operation and applications informa- tion. The data sheet must be read in conjunction with this demo manual for demonstration circuit 2637A. The LT3045EDD-1 is assembled in a 12-lead (3mm × 3mm) plastic DFN package with an exposed pad on the bottom- side of the IC. Proper board layout is essential for maxi- mum thermal performance.
Design files for this circuit board are available at http://www.analog.com/DC2637A
PERFORMANCE SUMMARY
Specifications are at TA = 25°C
PARAMETER| CONDITIONS| MIN TYP MAX|
UNITS
---|---|---|---
Input Voltage Range (VIN)| IOUT = 500mA, VOUT = 3.3V
IOUT = 2A, VOUT = 3.3V
| 3.8 20
3.8 5.5*
| VDC VDC
Output Voltage (VOUT)| VIN = 5V, IOUT = 2A| 3.19 3.29
3.39| VDC
Shutdown Input Current (IIN)| JP1 = OFF, VIN = 5V| 1| µA
The maximum input voltage for 2A load current is set by the 65°C temperature rise of LT3045-1 on the demo circuit. Higher input voltage can be reached if larger copper area or force-air cooling is applied. The output current is also limited by the differential of input and output voltage, please refer the data sheet for details.
QUICK START PROCEDURE
Demonstration circuit 2637A is easy to set up to evaluate the performance of four LT3045EDD-1s in parallel. Refer to Figure 1 for proper measurement equipment setup and follow the procedure below:
-
Connect the load between the VOUT and GND terminals
-
With the power off, connect the input power supply to the VIN and GND terminals
-
Make sure the shunt of JP1 is at ON option
-
Apply 8V across VIN to GND. Draw 2A of load cur- rent. The output voltage should be 3.29V ±3% (3.19V to 3.39V).
-
Vary VIN from 8V to 20V and the load current up to 2A.
NOTE : Make sure the power dissipation is below the thermal limit. -
Refer to Application Notes AN70 and AN159 for measuring output noise and PSRR.
PCB LAYOUT
Best PSRR Performance: PCB Layout for Input Trace
For applications utilizing the LT3045-1 for post-regulating switching
converters, placing a capacitor directly at the LT3045-1 input results in AC
current (at the switching fre- quency) flowing near the LT3045-1. Without
careful atten- tion to PCB layout, this relatively high frequency switching
current generates an electromagnetic field (EMF) that couples to the LT3045-1
output, thereby degrading its effective PSRR. While highly dependent on the
PCB, the switching pre-regulator, and the input capacitor size, among other
factors, the PSRR degradation can easily be 30dB at 1MHz. This degradation is
present even if the LT3045-1 is de-soldered from the board, because it effec-
tively degrades the PSRR of the PC board itself. While negligible for
conventional low PSRR LDOs, LT3045-1’s ultrahigh PSRR requires careful
attention to higher-order parasitics in order to realize the full performance
offered by the regulator.The LT3045-1 demo board alleviates this degradation
in PSRR by using a specialized layout technique. In Figure 2 , the input
trace (VIN) is highlighted in red, and in Figure 3 the return path (GND)
is also highlighted together with input capacitor C3. Normally when an AC
voltage is applied to the input of the board, AC current flows on this path,
thus generating EMF. This EMF couples to out- put capacitors (C1, C4, C6, C7)
and related traces, mak- ing the PSRR appear worse than it actually is.
With the input trace directly above the return path, the EMFs are in opposite directions and consequently cancel each otherout. Making sure these traces exactly overlap each other maximizes the cancellation effect and thus provides the maximum PSRR offered by the regulator.
PCB LAYOUT
Best AC Performance: PCB Layout for Output Capacitors C1, C4, C6 and C7
For ultrahigh PSRR performance, the LT3045-1 bandwidth is quite high (~1MHz), making it very close to the output capacitor’s self-resonance frequency (~1.6MHz). There- fore, it is very important to avoid adding extra impedance (ESL and ESR) outside the feedback loop. To that end, minimize the effects of PCB trace and solder inductance by Kelvin connecting OUTS and SET pin capacitor (CSET) GND directly to output capacitors (C2) terminals using split capacitor techniques. In parallel configuration, for each output cap, pad 4 connects to the OUTS pin, and pad 1 connects to the GND side of the SET pin capacitor. With only small current flowing through these connections, the impact of solder joint/PCB trace inductance on stability is eliminated. While the LT3045-1 is robust enough not to oscillate if the recommended layout is not followed, phase/gain margin and stability will degrade.
PCB LAYOUT
PARTS LIST
ITEM| QTY| REFERENCE| PART DESCRIPTION|
MANUFACTURER/PART NUMBER
---|---|---|---|---
Required Circuit Components
1| 4| C1, C4, C6, C7| CAP., 10µF, X5R, 25V, 10%, 1206| MURATA,
GJ831CR61E106KE83L
---|---|---|---|---
2| 1| C2| CAP., 22µF, 35V, 20%, 5X5.4mm| SUN ELECTRONIC INDUSTRIES CORP,
35CE22BSS
3| 3| C29, C30, C31| CAP., 0.47µF, X7R, 50V, 10%, 0805| MURATA,
GRM21BR71H474KA88L
4| 1| C3| CAP., 4.7µF, X7R, 50V, 10%, 1206| MURATA, GRM31CR71H475KA12L
5| 1| C5| CAP., 4.7µF, X7R, 25V, 10%, 1206| MURATA, GRM31CR71E475KA88L
6| 1| R18| RES., 200k, 1%, 1/10W, 0603| VISHAY, CRCW0603200KFKEA
7| 4| R2, R3, R8, R9| RES., 0.02Ω, 1%, 1/5W, 0603| VISHAY, RCWE060320L0FQEA
8| 4| R10, R12, R14, R16| RES., 249Ω, 1%, 1/10W, 0603| VISHAY,
CRCW0603249RFKEA
9| 1| R4| RES., 453k, 1%, 1/10W, 0603| VISHAY, CRCW0603453KFKEA
10| 1| R6| RES., 49.9k, 1%, 1/10W, 0603| VISHAY, CRCW060349K9FKEA
11| 1| R7| RES., 8.25k, 1%, 1/10W, 0805| VISHAY, CRCW06038K25FKEA
12| 4| U1, U2, U3, U4| IC, LT3045EDD-1 12PIN DFN 3X3MM| LINEAR TECHNOLOGY,
LT3045-1EDD#PB
Additional Demo Board Circuit Components
1| 1| C35, C40| CAP., OPTION, 1206|
---|---|---|---|---
2| 6| C26, C32, C34, C36, C37, C39| CAP., 0603, OPTION|
Hardware: For Demo Board Only
1| 5| E1, E2, E3, E4, E5| TEST POINT, TURRET, 0.094″, MTG. HOLE| MILL-MAX,
2501-2-00-80-00-00-07-0
---|---|---|---|---
2| 1| JP1| CONN., HDR, MALE, 2×3, 2mm, THT, STR| WURTH ELEKTRONIK, 62000621121
3| 1| XJP1| CONN., SHUNT, FEMALE, 2 POS, 2mm| WURTH ELEKTRONIK, 60800213421
4| 2| J1, J2| CONN., RF, BNC, RCPT, THT, STR, 5-PIN| AMPHENOL CONNEX, 112404
5| 4| MH1, MH2, MH3, MH4| STANDOFF, NYLON, SNAP-ON, 0.250″| WURTH ELEKTRONIK,
702931000
**SCHEMATIC DIAGRAM
**
ESD Caution
ESD (electrostatic discharge) sensitive device:
Charged devices and circuit boards can discharge without detection.
Although this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high-energy ESD. Therefore, proper
ESD precautions should be taken to avoid performance degradation or loss of
functionality.
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