MCS RV-3032-C7 Real Time Clock Module with I2C Bus Instruction Manual
- June 9, 2024
- MCS
Table of Contents
MCS RV-3032-C7 Real Time Clock Module with I2C Bus
RV-3032-C7
Application Manual
Application Manual
RV-3032-C7
DTCXO Temp. Compensated Real-Time Clock Module with I2C-Bus Interface
November 2022
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Micro Crystal DTCXO Temp. Compensated Real-Time Clock Module
RV-3032-C7
TABLE OF CONTENTS
1. OVERVIEW ……………………………………………………………………………………………………………………………………. 7
1.1. GENERAL DESCRIPTION…………………………………………………………………………………………………………. 8
1.2. APPLICATIONS ……………………………………………………………………………………………………………………….. 8
1.3. ORDERING INFORMATION ………………………………………………………………………………………………………. 8
2. BLOCK DIAGRAM………………………………………………………………………………………………………………………….. 9
2.1. PINOUT …………………………………………………………………………………………………………………………………. 10
2.2. PIN DESCRIPTION …………………………………………………………………………………………………………………. 10
2.3. FUNCTIONAL DESCRIPTION………………………………………………………………………………………………….. 11
2.4. DEVICE PROTECTION DIAGRAM …………………………………………………………………………………………… 12
3. REGISTER ORGANIZATION …………………………………………………………………………………………………………. 13
3.1. REGISTER CONVENTIONS …………………………………………………………………………………………………….. 13
3.2. REGISTER OVERVIEW …………………………………………………………………………………………………………… 14
3.3. CLOCK REGISTERS ………………………………………………………………………………………………………………. 17
3.4. CALENDAR REGISTERS ………………………………………………………………………………………………………… 18
3.5. ALARM REGISTERS ………………………………………………………………………………………………………………. 20
3.6. PERIODIC COUNTDOWN TIMER CONTROL REGISTERS ………………………………………………………… 21
3.7. STATUS REGISTER ……………………………………………………………………………………………………………….. 22
3.8. TEMPERATURE REGISTERS………………………………………………………………………………………………….. 23
3.9. CONTROL REGISTERS ………………………………………………………………………………………………………….. 25
3.10. TIME STAMP CONTROL REGISTER ……………………………………………………………………………………….. 28
3.11. CLOCK INTERRUPT MASK REGISTER …………………………………………………………………………………… 29
3.12. EVI CONTROL REGISTER ………………………………………………………………………………………………………. 30
3.13. TEMPERATURE THRESHOLDS REGISTERS…………………………………………………………………………… 31
3.14. TIME STAMP TLOW REGISTERS ……………………………………………………………………………………………. 32
3.15. TIME STAMP THIGH REGISTERS …………………………………………………………………………………………… 35
3.16. TIME STAMP EVI REGISTERS ………………………………………………………………………………………………… 38
3.17. PASSWORD REGISTERS……………………………………………………………………………………………………….. 42
3.18. EEPROM MEMORY CONTROL REGISTERS ……………………………………………………………………………. 43
3.19. RAM REGISTERS …………………………………………………………………………………………………………………… 44
3.20. CONFIGURATION EEPROM WITH RAM MIRROR REGISTERS…………………………………………………. 45
3.20.1. EEPROM PMU REGISTER ……………………………………………………………………………………………….. 45
3.20.2. EEPROM OFFSET REGISTER ………………………………………………………………………………………….. 46
3.20.3. EEPROM CLKOUT REGISTERS ……………………………………………………………………………………….. 47
3.20.4. EEPROM TEMPERATURE REFERENCE REGISTERS ……………………………………………………….. 49
3.20.5. EEPROM PASSWORD REGISTERS………………………………………………………………………………….. 50
3.20.6. EEPROM PASSWORD ENABLE REGISTER ………………………………………………………………………. 51
3.21. USER EEPROM ……………………………………………………………………………………………………………………… 51
3.22. REGISTER RESET VALUES SUMMARY ………………………………………………………………………………….. 52
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4. DETAILED FUNCTIONAL DESCRIPTION ………………………………………………………………………………………. 57 4.1. POWER ON RESET (POR)………………………………………………………………………………………………………. 57 4.2. AUTOMATIC BACKUP SWITCHOVER FUNCTION……………………………………………………………………. 58 4.2.1. SWITCHOVER DISABLED ………………………………………………………………………………………………… 59 4.2.2. DIRECT SWITCHING MODE (DSM) …………………………………………………………………………………… 59 4.2.3. LEVEL SWITCHING MODE (LSM)……………………………………………………………………………………… 60 4.3. TRICKLE CHARGER WITH CHARGE PUMP…………………………………………………………………………….. 61 4.4. PROGRAMMABLE CLOCK OUTPUT ………………………………………………………………………………………. 61 4.4.1. XTAL CLKOUT FREQUENCY SELECTION…………………………………………………………………………. 62 4.4.2. HF CLKOUT FREQUENCY SELECTION…………………………………………………………………………….. 62 4.4.3. CLKOUT FREQUENCY TRANSITIONS………………………………………………………………………………. 63 4.4.4. NORMAL CLOCK OUTPUT……………………………………………………………………………………………….. 63 4.4.5. INTERRUPT CONTROLLED CLOCK OUTPUT……………………………………………………………………. 63 4.4.6. INTERRUPT DELAY AFTER CLKOUT ON ………………………………………………………………………….. 64 4.4.7. CLKOUT OFF DELAY AFTER I2C STOP ……………………………………………………………………………. 64 4.4.8. CLOCK OUTPUT SCHEME……………………………………………………………………………………………….. 65 4.5. SETTING AND READING THE TIME ………………………………………………………………………………………… 66 4.5.1. SETTING THE TIME …………………………………………………………………………………………………………. 67 4.5.2. READING THE TIME ………………………………………………………………………………………………………… 67 4.6. EEPROM READ/WRITE ………………………………………………………………………………………………………….. 68 4.6.1. POR REFRESH (ALL CONFIGURATION EEPROM RAM) ………………………………………………… 68 4.6.2. AUTOMATIC REFRESH (ALL CONFIGURATION EEPROM RAM) ……………………………………. 68 4.6.3. UPDATE (ALL CONFIGURATION RAM EEPROM) ………………………………………………………….. 68 4.6.4. REFRESH (ALL CONFIGURATION EEPROM RAM)………………………………………………………… 68 4.6.5. WRITE TO ONE EEPROM BYTE (EEDATA (RAM) EEPROM) ………………………………………….. 69 4.6.6. READ ONE EEPROM BYTE (EEPROM EEDATA (RAM))…………………………………………………. 69 4.6.7. EEBUSY BIT ……………………………………………………………………………………………………………………. 70 4.6.8. EEF FLAG ……………………………………………………………………………………………………………………….. 71 4.6.9. EEPROM READ/WRITE CONDITIONS ………………………………………………………………………………. 71 4.6.10. USE OF THE CONFIGURATION REGISTERS ……………………………………………………………………. 72 4.7. INTERRUPT OUTPUT …………………………………………………………………………………………………………….. 73 4.7.1. SERVICING INTERRUPTS ……………………………………………………………………………………………….. 73 4.7.2. INTERRUPT SCHEME ……………………………………………………………………………………………………… 74 4.8. PERIODIC COUNTDOWN TIMER INTERRUPT FUNCTION ……………………………………………………….. 77 4.8.1. PERIODIC COUNTDOWN TIMER DIAGRAM………………………………………………………………………. 77 4.8.2. USE OF THE PERIODIC COUNTDOWN TIMER INTERRUPT ………………………………………………. 78 4.8.3. FIRST PERIOD DURATION ………………………………………………………………………………………………. 80 4.9. PERIODIC TIME UPDATE INTERRUPT FUNCTION ………………………………………………………………….. 81 4.9.1. PERIODIC TIME UPDATE DIAGRAM …………………………………………………………………………………. 81
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4.9.2. USE OF THE PERIODIC TIME UPDATE INTERRUPT …………………………………………………………. 82
4.10. ALARM INTERRUPT FUNCTION……………………………………………………………………………………………… 83
4.10.1. ALARM DIAGRAM ……………………………………………………………………………………………………………. 83 4.10.2.
USE OF THE ALARM INTERRUPT…………………………………………………………………………………….. 84 4.11. EXTERNAL
EVENT INTERRUPT FUNCTION ……………………………………………………………………………. 85 4.11.1. EXTERNAL
EVENT DIAGRAM ………………………………………………………………………………………….. 86 4.11.2. USE OF THE
EXTERNAL EVENT INTERRUPT …………………………………………………………………… 87 4.11.3. EDGE DETECTION
(ET = 00) ……………………………………………………………………………………………. 88 4.11.4. LEVEL DETECTION WITH
FILTERING (ET 00) ………………………………………………………………… 88 4.12. TEMPERATURE LOW INTERRUPT
FUNCTION………………………………………………………………………… 89 4.12.1. TEMPERATURE LOW DIAGRAM
………………………………………………………………………………………. 90 4.12.2. USE OF THE TEMPERATURE LOW
INTERRUPT ………………………………………………………………. 91 4.13. TEMPERATURE HIGH INTERRUPT
FUNCTION ……………………………………………………………………….. 92 4.13.1. TEMPERATURE HIGH DIAGRAM
……………………………………………………………………………………… 93 4.13.2. USE OF THE TEMPERATURE HIGH
INTERRUPT………………………………………………………………. 94 4.14. AUTOMATIC BACKUP SWITCHOVER
INTERRUPT FUNCTION ………………………………………………… 95 4.14.1. AUTOMATIC BACKUP SWITCHOVER
DIAGRAM ……………………………………………………………….. 95 4.14.2. USE OF THE AUTOMATIC BACKUP
SWITCHOVER INTERRUPT ……………………………………….. 96 4.15. POWER ON RESET INTERRUPT
FUNCTION …………………………………………………………………………… 97 4.15.1. POWER ON RESET DIAGRAM
…………………………………………………………………………………………. 97 4.15.2. USE OF THE POWER ON RESET
INTERRUPT ………………………………………………………………….. 98 4.16. VOLTAGE LOW INTERRUPT
FUNCTION…………………………………………………………………………………. 99 4.16.1. VOLTAGE LOW DIAGRAM
……………………………………………………………………………………………….. 99 4.16.2. USE OF THE VOLTAGE LOW
INTERRUPT………………………………………………………………………. 100 4.17. TIME STAMP EVI FUNCTION
………………………………………………………………………………………………… 101 4.17.1. TIME STAMP EVI SCHEME
…………………………………………………………………………………………….. 102 4.18. TIME STAMP TLOW FUNCTION
……………………………………………………………………………………………. 103 4.18.1. TIME STAMP TLOW SCHEME
………………………………………………………………………………………… 104 4.19. TIME STAMP THIGH
FUNCTION……………………………………………………………………………………………. 105 4.19.1. TIME STAMP THIGH
SCHEME………………………………………………………………………………………… 106 4.20. TEMPERATURE REFERENCE
ADJUSTMENT ……………………………………………………………………….. 107 4.20.1. TREF VALUE DETERMINATION
……………………………………………………………………………………… 107 4.21. TIME SYNCHRONIZATION
……………………………………………………………………………………………………. 109 4.21.1. STOP BIT FUNCTION
…………………………………………………………………………………………………….. 109 4.21.2. WRITING TO SECONDS
REGISTER ……………………………………………………………………………….. 111 4.21.3. ESYN BIT FUNCTION
…………………………………………………………………………………………………….. 112 4.22. USER PROGRAMMABLE PASSWORD
………………………………………………………………………………….. 114 4.22.1. ENABLE/DISABLE WRITE
PROTECTION…………………………………………………………………………. 114 4.22.2. CHANGING PASSWORD
………………………………………………………………………………………………… 115
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4.22.3. FLOWCHART…………………………………………………………………………………………………………………. 116 5.
TEMPERATURE COMPENSATION………………………………………………………………………………………………. 117
5.1. XTAL MODE FREQUENCIES…………………………………………………………………………………………………. 117 5.2.
COMPENSATION VALUES……………………………………………………………………………………………………. 117 5.3. AGING
CORRECTION …………………………………………………………………………………………………………… 118
5.3.1. OFFSET VALUE DETERMINATION …………………………………………………………………………………. 118 5.3.2.
MEASURING TIME ACCURACY AT CLKOUT PIN …………………………………………………………….. 119 5.4.
CLOCKING SCHEME ……………………………………………………………………………………………………………. 120 6. I2C
INTERFACE ………………………………………………………………………………………………………………………….. 121 6.1. BIT
TRANSFER ……………………………………………………………………………………………………………………. 121 6.2. START AND STOP
CONDITIONS ………………………………………………………………………………………….. 121 6.3. DATA VALID
………………………………………………………………………………………………………………………… 122 6.4. SYSTEM
CONFIGURATION…………………………………………………………………………………………………… 122 6.5. ACKNOWLEDGE
………………………………………………………………………………………………………………….. 123 6.6. SLAVE ADDRESS
………………………………………………………………………………………………………………… 124 6.7. WRITE OPERATION
……………………………………………………………………………………………………………… 124 6.8. READ OPERATION AT SPECIFIC
ADDRESS …………………………………………………………………………. 125 6.9. READ OPERATION
………………………………………………………………………………………………………………. 125 6.10. I2C-BUS IN SWITCHOVER
CONDITION………………………………………………………………………………….. 126 7. ELECTRICAL
SPECIFICATIONS………………………………………………………………………………………………….. 127 7.1. ABSOLUTE
MAXIMUM RATINGS ………………………………………………………………………………………….. 127 7.2. OPERATING
PARAMETERS …………………………………………………………………………………………………. 128 7.2.1. TEMPERATURE
COMPENSATION AND CURRENT CONSUMPTION ………………………………… 130 7.2.2. TYPICAL
CHARACTERISTICS ………………………………………………………………………………………… 131 7.3. XTAL OSCILLATOR
PARAMETERS………………………………………………………………………………………. 132 7.3.1. TIME ACCURACY VS.
TEMPERATURE CHARACTERISTICS ……………………………………………. 133 7.3.2. TIME ACCURACY 1 HZ
EXAMPLES ………………………………………………………………………………… 134 7.3.3. TEMPERATURE SENSOR
ACCURACY EXAMPLE …………………………………………………………… 135 7.4. POWER ON AC ELECTRICAL
CHARACTERISTICS ……………………………………………………………….. 136 7.5. BACKUP AND RECOVERY AC
ELECTRICAL CHARACTERISTICS ………………………………………… 138 7.6. I2C-BUS
CHARACTERISTICS………………………………………………………………………………………………… 139 8. TYPICAL
APPLICATION CIRCUITS……………………………………………………………………………………………… 140 8.1. NO BACKUP
SOURCE / EVENT INPUT NOT USED ………………………………………………………………… 140 8.2. NON-
RECHARGEABLE BACKUP SOURCE / EVENT INPUT USED (ACTIVE HIGH) …………………. 141 8.3.
RECHARGEABLE BACKUP SOURCE / EVENT INPUT USED (ACTIVE LOW) ………………………….. 142
8.4. CERACHARGETM BACKUP BATTERY / EVENT INPUT NOT USED …………………………………………. 143
8.5. NO BACKUP SOURCE / EVENT INPUT USED (“WAKE-UP” & “POWER SWITCH”) ………………….
144 9. PACKAGE………………………………………………………………………………………………………………………………….. 145 9.1.
DIMENSIONS AND SOLDER PAD LAYOUT……………………………………………………………………………. 145
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9.1.1. RECOMMENDED THERMAL RELIEF ………………………………………………………………………………. 145 9.2. MARKING AND PIN #1 INDEX……………………………………………………………………………………………….. 146 10. MATERIAL COMPOSITION DECLARATION & ENVIRONMENTAL INFORMATION …………………………. 147 10.1. HOMOGENOUS MATERIAL COMPOSITION DECLARATION ………………………………………………….. 147 10.2. MATERIAL ANALYSIS & TEST RESULTS ……………………………………………………………………………… 148 10.3. RECYCLING MATERIAL INFORMATION ……………………………………………………………………………….. 149 10.4. ENVIRONMENTAL PROPERTIES & ABSOLUTE MAXIMUM RATINGS ……………………………………. 150 11. SOLDERING INFORMATION……………………………………………………………………………………………………….. 151 12. HANDLING PRECAUTIONS FOR MODULES WITH EMBEDDED CRYSTALS …………………………………. 152 13. PACKING & SHIPPING INFORMATION………………………………………………………………………………………… 153 14. COMPLIANCE INFORMATION …………………………………………………………………………………………………….. 154 15. DOCUMENT REVISION HISTORY………………………………………………………………………………………………… 154
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RV-3032-C7
DTCXO Temp. Compensated Real-Time Clock (RTC) Module with I2C-Bus Interface
1. OVERVIEW
RTC module with built-in 32.768 kHz “Tuning Fork” crystal oscillator and HF
oscillator Counters for hundredths of seconds, seconds, minutes, hours,
weekday, date, month and year
o Automatic leap year correction: 2000 to 2099 Factory calibrated temperature
compensation Very High Time Accuracy
o ±2.5 ppm from -40 to +85°C o ±20 ppm from +85 to +105°C o Aging compensation
with Offset value Interrupt functions (1) o Periodic Countdown Timer o
Periodic Time Update (seconds, minutes) o Alarm for date, hours and minutes
settings o External Event with Time Stamp o Temperature Low with Time Stamp o
Temperature High with Time Stamp o Automatic Backup Switchover o Power On
Reset (POR) o Voltage Low Detection: typical 1.2 V (sampling 1 Hz) 16 Bytes of
User RAM and 32 Bytes of User EEPROM Configuration registers stored in EEPROM
and mirrored in RAM User programmable password for write protection I2C-bus
interface (up to 400 kHz) o 7-bit slave address = 1010001b (51h): read A3h,
write A2h Programmable Clock Output for peripheral devices o XTAL mode: 32.768
kHz, 1024 Hz, 64 Hz, 1 Hz o HF mode: 8192 Hz to 67.109 MHz in 8192 Hz steps o
Synchronized CLKOUT enable/disable and oscillator change o Selectable enable
via Interrupt functions o Selectable INT delay for MCU wake up o Selectable
CLKOUT-OFF delay for MCU sleep mode command Digital Thermometer (sampling 1
Hz) o ±3°C from -40 to +85°C o ±7°C from +85 to +105°C o Readable and
adjustable 12-bit temperature sensor: resolution 0.0625°C/step Trickle Charger
with Charge Pump for VBACKUP VDD and 1.75 V for TDK’s CeraChargeTM Wide
Timekeeping voltage range: 1.3 to 5.5 V (including temperature sensing and
compensation) Wide interface operating voltage: 1.4 to 5.5 V Very low current
consumption: 160 nA (VDD = 3.0 V, TA = 25°C) Operating temperature range: -40
to +85°C (supports extended range from +85°C to +105°C with limitations) Ultra
small and compact C7 package size (3.2 x 1.5 x 0.8 mm), RoHS-compliant and
100% lead-free Automotive qualification according to AEC-Q200 available
(1) The interrupt output pin INT also works in VBACKUP Power state.
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1.1. GENERAL DESCRIPTION
The RV-3032-C7 is a highly accurate real-time clock/calendar module due to its
built-in Thermometer and Digital Temperature Compensation circuitry (DTCXO).
The Temperature Compensation circuitry is factory calibrated and results in
highest time accuracy of ±2.5 ppm across the temperature range from -40 to
+85°C and a time accuracy of ±20 ppm for the extended range from +85°C to
+105°C, and additionally offers a non-volatile aging offset correction. The
RV-3032-C7 has the smallest package and the lowest current consumption among
all temperature compensated RTC modules. Due to its special architecture the
RV-3032-C7 provides a very low current consumption of 160 nA. The RV-3032-C7
CMOS real-time clock/calendar module includes automatic backup switching
circuitry, a trickle charger with charge pump, and offers full RTC
functionality with programmable counters, alarm, selectable interrupt, and
clock output capabilities for frequencies from 1 Hz to 67 MHz. The internal
EEPROM memory hosts all configuration settings and allows for additional user
memory. Addresses and data are transmitted via an I2C-bus interface for
communication with a host controller. The Address Pointer is incremented
automatically after each written or read data byte.
1.2. APPLICATIONS
The RV-3032-C7 RTC module combines key functions with outstanding performance
in an ultra-small ceramic package:
Factory calibrated Temperature Compensation with temperature measuring every
second Ultra-Low Power consumption Smallest RTC module (embedded XTAL) in an
ultra-small 3.2 x 1.5 x 0.8 mm lead-free ceramic package
These unique features make this product perfectly suitable for many applications:
Communication: IoT / Wearables / Wireless Sensors and Tags / Handsets
Automotive:
M2M / Navigation & Tracking Systems / Dashboard / Tachometers / Engine Controller
Car Audio & Entertainment Systems
Metering:
E-Meter / Heating Counter / Smart Meters / PV Converter / Utility metering
Outdoor:
ATM & POS systems / Surveillance & Safety systems / Ticketing Systems
Medical:
Glucose Meter / Health Monitoring Systems
Safety:
Security & Camera Systems / Door Lock & Access Control / Tamper Detection
Consumer:
Gambling Machines / TV & Set Top Boxes / White Goods
Automation:
PLC / Data Logger / Home & Factory Automation / Industrial and Consumer Electronics
1.3. ORDERING INFORMATION
Example:
RV-3032-C7 TA QC
Code
Operating temperature range
TA (Standard)
-40 to +85°C
- Supports extended range from +85°C to +105°C with limitations.
Code QC (Standard) QA
Qualification Commercial Grade Automotive Grade AEC-Q200
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2. BLOCK DIAGRAM
RV-3032-C7
VBACKUP VDD VSS SCL SDA
CLKOUT INT EVI
1
POWER
MANAGEMENT
6
UNIT
5
8 I2C-BUS
2 INTERFACE
XTAL OSC.
T-SENSOR TEMP. COMP.
DIVIDER HF OSC.
7
3
INPUT
OUTPUT
CONTROL 4
SYSTEM CONTROL
LOGIC
RESET
RAM
RAM
100th Seconds 00
PW 0
39
Seconds
PW 1
Minutes
PW 2
Hours
PW 3
Weekday
EEADDR
Date
EEDATA
Month
EECMD
3F
Year
07
Minutes Alarm 08
Hours Alarm
16 Bytes of
40
user RAM
4F
Date Alarm
Timer Value 0
Configuration EEPROM
Timer Value 1
with RAM mirror
Status Temperature LSBs
EEPROM PMU C0
Temperature MSBs 0F EEPROM Offset
Control 1
10 EEPROM Clkout 1
Control 2
EEPROM Clkout 2
Control 3
EEPROM TRef. 0
Time Stamp Control
EEPROM TRef. 1
Clock Int. Mask
EEPW 0
EVI Control
EEPW 1
TLow Threshold
EEPW 2
THigh Threshold TS TLow Count 18
EEPW 3
EEPWE
CA
Time Stamp TLow 19 Seconds to Year 1E
User EEPROM
TS THigh Count 1F
Time Stamp THigh 20 Seconds to Year 25
TS EVI Count 26 Time Stamp EVI 27
32 Bytes of user EEPROM
(CBh to EAh)
100th Secs. to Year 2D
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2.1. PINOUT
RV-3032-C7 Package: (top view)
8
5
3032
1
4
RV-3032-C7
1
VBACKUP
2
SDA
3
INT
4
EVI
5
VSS
6
VDD
7
CLKOUT
8
SCL
2.2. PIN DESCRIPTION
Symbol VBACKUP SDA INT
Pin # 1 2 3
EVI
4
VSS
5
VDD
6
CLKOUT
7
SCL
8
Description
Backup Supply Voltage. When the backup switchover function is not needed,
VBACKUP must be tied to VSS with a 10 k resistor. I2C Serial Data Input-
Output; open-drain; requires pull-up resistor. In VBACKUP Power state, the SDA
pin is disabled (high impedance). Interrupt Output; open-drain; active LOW;
requires pull-up resistor; used to output Periodic Countdown Timer, Periodic
Time Update, Alarm, Temperature Low, Temperature High, External Event, Voltage
Low, Automatic Backup Switchover and Power On Reset Interrupt signals.
Interrupt output also works in VBACKUP Power state. External Event Input; used
for interrupt generation, interrupt driven clock output and time stamp
function. Remains active also in VBACKUP Power state. This pin must not be
left floating.
Ground.
Power Supply Voltage.
Clock Output; push-pull; Normal and Interrupt driven clock output can be
activated concurrently. 1. Normal clock output is controlled by the NCLKE bit
(EEPROM C0h). When NCLKE is set to 0 (default), the square wave output is
enabled on the CLKOUT pin. When NCLKE bit is set to 1, the CLKOUT pin is LOW,
if not enabled by the interrupt driven clock output (CLKF = 0). 2. Interrupt
driven clock output is controlled by an interrupt event. When CLKIE bit
(address 11h) is set to 1 the occurrence of the interrupt selected in the
Clock Interrupt Mask Register (address 14h) allows the square wave output on
the CLKOUT pin (for waking up the MCU). Writing 0 to CLKIE will disable new
interrupts from driving square wave on CLKOUT. When CLKF flag is cleared, the
CLKOUT pin is LOW. An Interrupt Delay after CLKOUT on can be enabled with bit
INTDE (address 14h) (for waking up the MCU). A CLKOUT switch off delay after
I2C STOP can be selected and enabled by bits CLKD and CLKDE (registers 14h and
15h) (if the MCU wants to put itself into sleep mode).
When OS bit is set to 0 (EEPROM C3h) and depending of the settings in the FD
field (EEPROM C3h) the CLKOUT pin can drive the square wave of 32.768 kHz,
1024 Hz, 64 Hz or 1 Hz. When OS bit is set to 1 (EEPROM C3h) and depending of
the settings in the HFD field (EEPROM C2h and C3h) the CLKOUT pin can drive
the square wave of a frequency between 8192 Hz to 67.109 MHz in 8192 Hz steps.
In VBACKUP Power state, the CLKOUT pin is LOW. If this pin is not used it can
be left floating; do not connect to a Supply Voltage or GND, as this is a
digital push-pull output. I2C Serial Clock Input; requires pull-up resistor.
In VBACKUP Power state, the SCL pin is disabled.
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2.3. FUNCTIONAL DESCRIPTION
The RV-3032-C7 is a high accurate, ultra-low power CMOS based Real-Time-Clock
Module that include a 32.768 kHz Crystal and an HF oscillator. The Xtal 32.768
kHz clock itself and the frequencies from the HF oscillator are not
temperature compensated. The very high Time Accuracy and stability of ±2.5 ppm
over the temperature range from -40°C to +85°C and of ±20 ppm for the extended
range from +85°C to +105°C is achieved by the built-in Digital Temperature
Compensation circuitry (DTCXO). The factory calibrated correction values are
located in the EEPROM and are not accessible for the user. Additionally, there
is an EEPROM Offset Register customer use for aging correction.
The RV-3032-C7 includes an Automatic Backup switchover function and a Trickle
Charger with Charge Pump. The
interrupt output pin INT is also working in VBACKUP Power state. The clock
output on CLKOUT pin can be enabled normally via command over I2C interface or
can be interrupt driven. The configuration registers are stored permanently in
EEPROM and mirrored in RAM in order that the RTC module is still configured
correctly even after power down. For safety against inadvertent overwriting,
the time, control and configuration registers can be protected by a User
Programmable Password.
The RV-3032-C7 provides standard Clock & Calendar function including 100th
seconds, seconds, minutes, hours (24 hour mode), weekday, date, month, year
(with leap year correction) and interrupt functions for the Periodic Countdown
Timer, Periodic Time Update, Alarm, Temperature Low, Temperature High,
External Event, Voltage Low, Automatic Backup Switchover and Power On Reset
Interrupt signals. All registers are accessible via I2C-bus (2-wire
Interface). Beside the standard RTC functions, it contains an integrated
12-bit Temperature Sensor with a readable Temperature Value in °C with a
resolution of 0.0625°C/step and an adjustable Temperature Reference value. It
also includes Time Stamp functions for the External Event, Temperature Low,
and Temperature High Interrupt functions. The Interrupt and Time Stamp
functions are also working in VBACKUP Power state. The module also provides 16
Bytes of User RAM and 32 Bytes of User Memory EEPROM. Another RAM Byte can be
used as User RAM when the Alarm function is not needed (Minutes Alarm,
register 08h), another Byte if the Periodic Countdown Timer is not used (Timer
Value 0, register 0Bh) and 2 further Bytes when the Temperature Thresholds are
not needed (Thresholds TLT and THT, registers 16h and 17h).
The RAM registers are accessed by selecting a register address and then performing read or write operations. Multiple reads or writes may be executed in a single access, with the address automatically incrementing after each byte. When address is automatically incremented, wrap around occurs from address FFh to address 00h (see figure below). All registers are designed as addressable 8-bit registers despite the fact that not all registers and bits are implemented.
Handling RAM address registers:
Address 00h 01h 02h 03h : FDh FEh FFh
autoincrement
wrap around
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Micro Crystal DTCXO Temp. Compensated Real-Time Clock Module
2.4. DEVICE PROTECTION DIAGRAM
VBACKUP
1
SDA 2
INT 3
EVI 4
8 SCL
7 CLKOUT
6
VDD
5
VSS
RV-3032-C7
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Micro Crystal DTCXO Temp. Compensated Real-Time Clock Module
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3. REGISTER ORGANIZATION
RAM Registers at addresses 00h to 4Fh are accessed by selecting a register
address and then performing read or write operations. Multiple reads or writes
may be executed in a single access, with the address automatically
incrementing after each byte.
The Configuration Registers at addresses C0h to CAh are memorized in EEPROM
and mirrored in RAM. For the RAM mirror, multiple reads or writes may be
executed in a single access, with the address automatically incrementing after
each byte.
There are 32 Bytes of non-volatile user memory EEPROM at addresses CBh to EAh
for general use.
The tables in section REGISTER OVERVIEW summarize the function of each
register.
3.1. REGISTER CONVENTIONS
The conventions in this table serve as a key for the register overview and individual register diagrams:
Convention (Conv.)
Description
R W R/WP WP
*WP
Prot.
Read only. Writing to this register has no effect. Write only. Returns 0 when
read.
Read: Always readable. Write: Can be write-protected by password.
Write only. Returns 0 when read. Can be write-protected by password. EEPW
registers: Can be write-protected by password. RAM mirror is Write only.
Returns 0 when read. EEPROM can be READ when unlocked. Protected. Writing to
this register has no effect.
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3.2. REGISTER OVERVIEW
After reset, all registers are set according to Table in section REGISTER
RESET VALUES SUMMARY.
Register Definitions; RAM, Address 00h to 25h:
Address
Function
Conv.
00h
100th Seconds
R
01h
Seconds
R/WP
02h
Minutes
R/WP
03h
Hours
R/WP
04h
Weekday
R/WP
05h
Date
R/WP
06h
Month
R/WP
07h
Year
R/WP
08h
Minutes Alarm
R/WP
09h
Hours Alarm
R/WP
0Ah
Date Alarm
R/WP
0Bh
Timer Value 0
R/WP
0Ch
Timer Value 1
R/WP
0Dh
Status
R/WP
0Eh
Temperature LSBs R/WP
0Fh
Temperature MSBs R
10h
Control 1
R/WP
11h
Control 2
R/WP
12h
Control 3
R/WP
13h
Time Stamp Contr. R/WP
14h
Clock Int. Mask
R/WP
15h
EVI Control
R/WP
16h
TLow Threshold
R/WP
17h
THigh Threshold R/WP
18h
TS TLow Count
R
19h
TS TLow Seconds
R
1Ah
TS TLow Minutes
R
1Bh
TS TLow Hours
R
1Ch
TS TLow Date
R
1Dh
TS TLow Month
R
1Eh
TS TLow Year
R
1Fh
TS THigh Count
R
20h
TS THigh Seconds R
21h
TS THigh Minutes
R
22h
TS THigh Hours
R
23h
TS THigh Date
R
24h
TS THigh Month
R
25h
TS THigh Year
R
Read only. Always 0. – Bit not implemented. Will return a 0 when read.
Bit 7 80 80
AE_M AE_H AE_D 128
THF
CLKD CLKDE
128 80
128 80
Bit 6
Bit 5
Bit 4
Bit 3
40
20
10
8
40
20
10
8
40
20
10
8
20
10
8
20
10
8
10
8
40
20
10
8
40
20
10
8
20
10
8
20
10
8
64
32
16
8
2048
TLF
UF
TF
AF
TEMP [3:0]
EEF
TEMP [11:4]
–
GP0 USEL
TE
CLKIE
UIE
TIE
AIE
–
–
BSIE
THE
–
EVR
THR
TLR
INTDE CEIE
CAIE
CTIE
EHL
ET
TLT
THT
64
32
16
8
40
20
10
8
40
20
10
8
20
10
8
20
10
8
10
8
40
20
10
8
64
32
16
8
40
20
10
8
40
20
10
8
20
10
8
20
10
8
10
8
40
20
10
8
Bit 2
4 4 4 4 4 4 4 4 4 4 4 4 1024 EVF EEbusy
Bit 1
2 2 2 2 2 2 2 2 2 2 2 2 512 PORF CLKF
Bit 0
1 1 1 1 1 1 1 1 1 1 1 1 256 VLF BSF
EERD EIE TLE
EVOW CUIE
TD
GP1 STOP
THIE
TLIE
THOW TLOW
CTHIE CTLIE
ESYN
4
2
1
4
2
1
4
2
1
4
2
1
4
2
1
4
2
1
4
2
1
4
2
1
4
2
1
4
2
1
4
2
1
4
2
1
4
2
1
4
2
1
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Register Definitions; RAM, Address 26h to FFh:
Address
Function
26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh to 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh
40h to 4Fh
50h to BFh CBh to FFh
TS EVI Count TS EVI 100th Secs. TS EVI Seconds TS EVI Minutes TS EVI Hours TS EVI Date TS EVI Month TS EVI Year RESERVED Password 0 Password 1 Password 2 Password 3 EE Address EE Data EE Command User RAM (16 Bytes) RESERVED RESERVED
Read only. Always 0.
Conv.
R R R R R R R R Prot. W W W W R/WP R/WP WP
R/WP
Prot. Prot.
Bit 7
128 80 80
Bit 6
64 40 40 40 40
Bit 5
32 20 20 20 20 20 20
Bit 4
Bit 3
16
8
10
8
10
8
10
8
10
8
10
8
10
8
10
8
RESERVED
PW [7:0]
PW [15:8]
PW [23:16]
PW [31:24]
EEADDR
EEDATA
EECMD
16 Bytes of User RAM
RESERVED RESERVED
Bit 2
4 4 4 4 4 4 4 4
Bit 1
2 2 2 2 2 2 2 2
Bit 0
1 1 1 1 1 1 1 1
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Micro Crystal DTCXO Temp. Compensated Real-Time Clock Module
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Register Definitions; Configuration EEPROM with RAM mirror, Address C0h to CAh:
Address
Function
Conv. Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
C0h
EEPROM PMU
R/WP
–
NCLKE
BSM
TCR
C1h
EEPROM Offset R/WP PORIE VLIE
OFFSET
C2h
EEPROM Clkout 1
R/WP
C3h
EEPROM Clkout 2
R/WP OS
FD
C4h
EEPROM TReference 0
R/WP
C5h
EEPROM TReference 1
R/WP
C6h
EEPROM Password 0
*WP
C7h
EEPROM Password 1
*WP
C8h
EEPROM Password 2
*WP
C9h
EEPROM Password 3
*WP
CAh
EEPROM PW Enable
WP
HFD [7:0] TREF [7:0] TREF [15:8] EEPW [7:0] EEPW [15:8] EEPW [23:16] EEPW [31:24] EEPWE
HFD [12:8]
– Bit not implemented. Will return a 0 when read. *WP: The EEPW registers can
be write-protected by password.
RAM mirror is Write only. Returns 0 when read. EEPROM can be READ when
unlocked.
Bit 1
Bit 0
TCM
Register Definitions; User EEPROM, Address CBh to EAh:
Address CBh to EAh
Function
User EEPROM (32 Bytes)
Conv. R/WP
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
32 Bytes of non-volatile User EEPROM
Bit 1
Bit 0
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3.3. CLOCK REGISTERS
00h 100th Seconds This register holds the count of hundredths of seconds, in
two binary coded decimal (BCD) digits. Values will be from 00 to 99. Read
only. Writing to this register has no effect.
Address 00h Bit 7:0
Function 100th Seconds Reset Symbol
100th Seconds
Conv. R
Bit 7 80 0
Bit 6 40 0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value 00 to 99
Description
Holds the count of hundredths of seconds, coded in BCD format. When STOP bit
is set to 1 or when writing to the Seconds register or when ESYN bit is 1 in
case of an External Event detection on EVI pin the 100th Seconds register
value is cleared to 00 (see TIME SYNCHRONIZATION).
01h Seconds This register holds the count of seconds, in two binary coded
decimal (BCD) digits. Values will be from 00 to 59.
Read: Always readable. Write: Can be write-protected by password.
Address 01h Bit 7
6:0
Function Seconds Reset Symbol
Seconds
Conv. R/WP
Bit 7
0
Bit 6 40 0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value 0
00 to 59
Description
Read only. Always 0.
Holds the count of seconds, coded in BCD format. When writing to the Seconds
register the 100th Seconds register is cleared to 00 (similar to ESYN Bit
function). When STOP bit is 1 the Seconds register value remains unchanged
because 1 Hz clock is stopped (see TIME SYNCHRONIZATION).
02h Minutes This register holds the count of minutes, in two binary coded
decimal (BCD) digits. Values will be from 00 to 59.
Read: Always readable. Write: Can be write-protected by password.
Address
02h
Bit 7 6:0
Function Minutes Reset
Symbol Minutes
Conv. R/WP
Bit 7
0
Bit 6 40 0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Value 0
00 to 59
Description Read only. Always 0. Holds the count of minutes, coded in BCD format.
Bit 1 2 0
Bit 0 1 0
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03h Hours This register holds the count of hours, in two binary coded
decimal (BCD) digits. Values will be from 00 to 23.
Read: Always readable. Write: Can be write-protected by password.
Address
03h
Bit 7:6 5:0
Function Hours Reset
Symbol Hours
Conv. R/WP
Bit 7
0
Bit 6
0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Value 0
00 to 23
Description Read only. Always 0. Holds the count of hours, coded in BCD format.
Bit 1 2 0
Bit 0 1 0
3.4. CALENDAR REGISTERS
04h Weekday This register holds the current day of the week. Each value
represents one weekday that is assigned by the user. Values will range from 0
to 6. The weekday counter is simply a 3-bit counter which counts up to 6 and
then resets to 0. Read: Always readable. Write: Can be write-protected by
password.
Address 04h
Function Weekday Reset
Bit
Symbol
7:3
2:0
Weekday
Weekday Weekday 1 Default value Weekday 2 Weekday 3 Weekday 4 Weekday 5 Weekday 6 Weekday 7
Conv. R/WP
Bit 7 0
Value 0
0 to 6 Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2 4 0
Description Read only. Always 0. Holds the weekday counter value.
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0 0 0 0 1 1 1
Bit 1 2 0
Bit 1 0 0 1 1 0 0 1
Bit 0 1 0
Bit 0 0 1 0 1 0 1 0
05h Date This register holds the current day of the month, in two binary
coded decimal (BCD) digits. Values will range from 01
to 31. Leap years are correctly handled from 2000 to 2099.
Read: Always readable. Write: Can be write-protected by password.
Address 05h
Bit 7:6 5:0
Function Date Reset
Symbol Date
Conv. R/WP
Bit 7
0
Bit 6
0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Value 0
01 to 31
Description
Read only. Always 0. Holds the current date of the month, coded in BCD format.
Default value = 01 (01 is a valid date)
Bit 0 1 1
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Micro Crystal DTCXO Temp. Compensated Real-Time Clock Module
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06h Month This register holds the current month, in two binary coded decimal
(BCD) digits. Values will range from 01 to 12.
Read: Always readable. Write: Can be write-protected by password.
Address 06h
Function Month Reset
Bit
Symbol
7:5
4:0
Month
Months January Default value February March April May June July August September October November December
Conv. R/WP
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Value 0
01 to 12
Description Read only. Always 0. Holds the current month, coded in BCD format.
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0 0 0 0 0 0 0 0 0 1 1 1
Bit 3 0 0 0 0 0 0 0 1 1 0 0 0
Bit 2 0 0 0 1 1 1 1 0 0 0 0 0
Bit 1 2 0
Bit 1 0 1 1 0 0 1 1 0 0 0 0 1
Bit 0 1 1
Bit 0 1 0 1 0 1 0 1 0 1 0 1 0
07h Year This register holds the current year, in two binary coded decimal
(BCD) digits. Values will range from 00 to 99. Leap
years are correctly handled from 2000 to 2099.
Read: Always readable. Write: Can be write-protected by password.
Address 07h
Bit 7:0
Function Year Reset
Symbol Year
Conv. R/WP
Bit 7 80 0
Bit 6 40 0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value
Description
00 to 99 Holds the current year, coded in BCD format. Default value = 00
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Rev. 1.2
Micro Crystal DTCXO Temp. Compensated Real-Time Clock Module
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3.5. ALARM REGISTERS
08h Minutes Alarm This register holds the Minutes Alarm Enable bit AE_M and
the alarm value for minutes, in two binary coded decimal (BCD) digits. Values
will range from 00 to 59. Read: Always readable. Write: Can be write-protected
by password.
Address 08h Bit 7 6:0
Function Minutes Alarm Reset Symbol
AE_M
Minutes Alarm
Conv. R/WP
Bit 7 AE_M
0
Bit 6 40 0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value
Description
Minutes Alarm Enable bit. Enables alarm together with AE_H and AE_D (see USE OF THE ALARM INTERRUPT).
0
Enabled. Default value
1
Disabled.
00 to 59 Holds the alarm value for minutes, coded in BCD format.
09h Hours Alarm This register holds the Hours Alarm Enable bit AE_H and the
alarm value for hours, in two binary coded decimal
(BCD) digits. Values will range from 00 to 23.
Read: Always readable. Write: Can be write-protected by password.
Address 09h Bit
7
6 5:0
Function Hours Alarm Reset Symbol
AE_H
Hours Alarm
Conv. R/WP
Bit 7 AE_H
0
Bit 6
0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value
Description
Hours Alarm Enable bit. Enables alarm together with AE_M and AE_D (see USE OF THE ALARM INTERRUPT).
0
Enabled. Default value
1
Disabled.
0
Read only. Always 0.
00 to 23 Holds the alarm value for hours, coded in BCD format.
0Ah Date Alarm This register holds the Date Alarm Enable bit AE_D and the
alarm value for the date, in two binary coded decimal
(BCD) digits. Values will range from 01 to 31. Leap years are correctly
handled from 2000 to 2099.
Read: Always readable. Write: Can be write-protected by password.
Address 0Ah
Function Date Alarm Reset
Conv. R/WP
Bit 7 AE_D
0
Bit 6
0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Bit
Symbol
Value
Description
7
AE_D
Date Alarm Enable bit. Enables alarm together with AE_M and AE_H (see USE OF THE ALARM INTERRUPT).
0
Enabled. Default value
1
Disabled.
6
0
Read only. Always 0.
Holds the alarm value for the date, coded in BCD format.
5:0
Date Alarm
01 to 31 If the Date Alarm is to be used, the invalid value (00) must be replaced with a valid one (01 to 31). (1)
(1) Note that an alarm is never generated after POR because of the default values AE_D = 0 = enabled, Date = 01 (valid)
and Date Alarm = 00h (not valid).
November 2022
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3.6. PERIODIC COUNTDOWN TIMER CONTROL REGISTERS
0Bh Timer Value 0 This register is used to set the lower 8 bits of the 12
bit Timer Value (preset value) for the Periodic Countdown Timer. This value
will be automatically reloaded into the Countdown Timer when it reaches zero.
This allows for periodic timer interrupts (see calculation below). Read:
Always readable. Write: Can be write-protected by password.
Address 0Bh Bit
7:0
Function Timer Value 0 Reset Symbol
Timer Value 0
Conv. R/WP
Bit 7 128
0
Value
00h to FFh
Bit 6 64 0
Bit 5 32 0
Bit 4 16 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Description
The Timer Value for the Periodic Countdown Timer in binary format (lower 8
bit) (see USE OF THE PERIODIC COUNTDOWN TIMER). When read, only the preset
value is returned and not the current value. When the Periodic Countdown Timer
Interrupt function is not used, register 0Bh can be used as RAM byte.
0Ch Timer Value 1 This register is used to set the upper 4 bits of the 12 bit Timer Value (preset value) for the Periodic Countdown Timer. This value will be automatically reloaded into the Countdown Timer when it reaches zero. This allows for periodic timer interrupts (see calculation below). Read: Always readable. Write: Can be write-protected by password.
Address 0Ch
Bit 7:4 3:0
Function Timer Value 1 Reset
Symbol
Timer Value 1
Conv. R/WP
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3 2048
0
Bit 2 1024
0
Bit 1 512
0
Bit 0 256
0
Value 0
0h to Fh
Description
Read only. Always 0.
The Timer Value for the Periodic Countdown Timer in binary format (upper 4
bit) (see USE OF THE PERIODIC COUNTDOWN TIMER). When read, only the preset
value is returned and not the current value.
Countdown Period in seconds:
Countdown
Period =
Timer Value Timer Clock Frequency
November 2022
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Rev. 1.2
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3.7. STATUS REGISTER
0Dh Status This register is used to detect the occurrence of various
interrupt events and reliability problems in internal data. Note that flags
are read/clear only. Read: Always readable. Write: Can be write-protected by
password.
Address 0Dh
Function Status Reset
Conv. R/WP
Bit 7 THF
0
Bit 6 TLF
0
Bit 5 UF 0
Bit 4 TF 0
Bit 3 AF 0
Bit 2 EVF
X
Bit 1 PORF
1
Bit 0 VLF
0
Bit
Symbol
Value
Description
Temperature High Flag (see TEMPERATURE HIGH INTERRUPT FUNCTION)
7
THF
0
No event detected.
If set to 0 beforehand, indicates the occurrence of a temperature that is
1
above the stored Temperature High Threshold value THT. The value 1 is retained until a 0 is written by the user. (1)
THF is also cleared to 0 when writing 1 to the THR bit.
Temperature Low Flag (see TEMPERATURE LOW INTERRUPT FUNCTION)
6
TLF
0
No event detected.
If set to 0 beforehand, indicates the occurrence of a temperature that is
1
below the stored Temperature Low Threshold value TLT. The value 1 is retained until a 0 is written by the user. (1)
TLF is also cleared to 0 when writing 1 to the TLR bit.
Periodic Time Update Flag (see PERIODIC TIME UPDATE INTERRUPT FUNCTION)
5
UF
0
No event detected.
1
If set to 0 beforehand, indicates the occurrence of a Periodic Time Update Interrupt event. The value 1 is retained until a 0 is written by the user.
Periodic Countdown Timer Flag
(see PERIODIC COUNTDOWN TIMER INTERRUPT FUNCTION)
4
TF
0
No event detected.
If set to 0 beforehand, indicates the occurrence of a Periodic Countdown
1
Timer Interrupt event. The value 1 is retained until a 0 is written by the
user.
Alarm Flag (see ALARM INTERRUPT FUNCTION)
0
No event detected.
3
AF
2
EVF
If set to 0 beforehand, indicates the occurrence of an Alarm Interrupt
1
event. The value 1 is retained until a 0 is written by the user. Hint: The flag is set only on increment to a matched case (and not all the
time it is equal).
External Event Flag (see EXTERNAL EVENT INTERRUPT FUNCTION)
The Reset value X depends on the voltage on the EVI pin at POR and has
to be cleared by writing a 0 to the bit. Because EHL = 0 at POR, the low
X
level is regarded as an External Event Interrupt.
If X = 1, a LOW level was detected on EVI pin.
If X = 0, no LOW level was detected on EVI pin.
0
No event detected.
1
If set to 0 beforehand, indicates the occurrence of an External Event. The value 1 is retained until a 0 is written by the user.
Power On Reset Flag (see POWER ON RESET INTERRUPT FUNCTION)
0
No VDD startup from below VPOR (0.9 V) in VDD Power state detected.
1
PORF
If set to 0 beforehand, indicates that a VDD startup from below VPOR (0.9 V) in VDD Power state has occurred. The data in the device are no longer
1
valid and all registers must be initialized. The value 1 is retained until a 0 is
written by the user. At power up (POR) the value is set to 1, the user has to write 0 to the flag to use it.
Voltage Low Flag (see VOLTAGE LOW INTERRUPT FUNCTION)
0
VLF
0
No voltage drop of the internal voltage below VLOW detected (VDD or VBACKUP). At power on (POR) the VLF flag is automatically cleared to 0.
If set to 0 beforehand, indicates a voltage drop below VLOW (typical 1.2 V).
The sampling frequency is 1 Hz. The data in the device may no longer be
1
valid and all registers should be reinitialized. The value 1 is retained until a 0 is written by the user.
If the internal voltage is below VLOW, the temperature compensation is
stopped, CLKOUT is LOW and the I2C interface is disabled (VDD < 1.4 V).
(1) Note that the THF and TLF flags are always reset whenever the register 0Dh
Status is written to (using 0s or 1s).
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Rev. 1.2
Micro Crystal DTCXO Temp. Compensated Real-Time Clock Module
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3.8. TEMPERATURE REGISTERS
0Eh Temperature LSBs This register hosts the 4 least significant bits (LSBs)
of the Temperature value TEMP [11:0] in two’s complement format (fractional
part). The register is also used to detect the occurrence of various interrupt
events and reliability problems in internal data. Note that the flags (EEF,
CLKF and BSF) are read/clear only. Read: Always readable. Write: Can be write-
protected by password.
Address 0Eh Bit 7:4
3
2
1 0
Function Temperature LSBs Reset
Conv. R/WP
Symbol
TEMP [3:0]
EEF EEbusy CLKF BSF
Bit 7
Bit 6
Bit 5
TEMP [3:0] 0h Xh
Bit 4
Bit 3 EEF
0
Bit 2
EEbusy 1 0
Bit 1 CLKF
0
Bit 0 BSF
0
Value
Description
0h to Fh
Fractional part of the Temperature value TEMP [11:0] in two’s complement format. (Read Only) Stores the last value of the measured internal temperature. Allows the higher measurement resolution of 1/16 = 0.0625°C. See table below (see also TEMPERATURE REFERENCE ADJUSTMENT). The internal temperature sensing itself is carried out automatically every second. One second after POR, the first temperature value (Xh) is available. Hint: The integer part TEMP [11:4] in register Temperature MSBs is automatically compared to the TLow and THigh Thresholds (see TEMPERATURE THRESHOLDS REGISTERS).
EEPROM Memory Write Access Failed Flag (see EEF FLAG)
0
Previous write access was successful.
If set to 0 beforehand, indicates that the EEPROM write access has failed
1
because VDD has dropped below VDD:EEF (1.3 V). The value 1 is retained
until a 0 is written by the user.
EEPROM Memory Busy Status Bit (Read Only)
(see EEBUSY BIT)
0
The transfer is finished.
Indicates that the EEPROM is currently handling a read or write request
and will ignore any further commands until the current one is finished.
1
At power up (POR) a refresh is automatically generated. The time of this
first refreshment is tPREFR = ~66 ms. After the refreshment is finished; EEbusy is cleared to 0 automatically.
Clock Output Interrupt Flag (see INTERRUPT CONTROLLED CLOCK OUTPUT)
0
No event detected.
If set to 0 beforehand, indicates the occurrence of an interrupt driven clock
1
output on CLKOUT pin. The value 1 is retained until a 0 is written by the
user.
Backup Switch Flag (see AUTOMATIC BACKUP SWITCHOVER FUNCTION)
No backup switchover detected. At power up (POR) this flag is
0
automatically cleared to 0. When the backup switchover function is
disabled (BSM field = 00 or 11) BSF is always logic 0.
If set to 0 beforehand, indicates that a switchover from main power VDD to
1
VBACKUP has occurred. The value 1 can be cleared by writing a 0 to the bit if
RTC module is in VDD Power state.
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0Fh Temperature MSBs This register hosts the 8 most significant bits (MSBs)
of the Temperature value TEMP [11:0] in two’s complement format (integer
part).
Read only. Writing to this register has no effect.
Address 0Fh Bit
7:0
Function
Conv.
Temperature MSBs R
Reset
Symbol
TEMP [11:4]
Bit 7
Value
00h to FFh
Bit 6
Bit 5
Bit 4
Bit 3
TEMP [11:4] 00h XXh
Bit 2
Bit 1
Bit 0
Description
Integer part of the Temperature value TEMP [11:0] in two’s complement format.
(Read Only) Stores the last value of the measured internal temperature with
1°C resolution in two’s complement format. See table below (see also
TEMPERATURE REFERENCE ADJUSTMENT). The internal temperature sensing itself is
carried out automatically every second. One second after POR, the first
temperature value (XXh) is available. The TEMP [11:4] value is automatically
compared to the TLow and THigh Thresholds (see TEMPERATURE THRESHOLDS
REGISTERS).
Temperature/Data relationship:
Address
Function
0Eh
Temperature LSBs
0Fh
Temperature MSBs
Conv. R/WP
R
Bit 7 2-1 Sign
Bit 6 2-2 26
Bit 5 2-3 25
Bit 4 2-4 24
Bit 3
EEF 23
Bit 2
EEbusy 22
Bit 1
CLKF 21
Bit 0
BSF 20
TEMP (12 bits) examples:
TEMP [11:0] value 0111’1111’1111
Hexadecimal 7FF
Decimal 2047
Signed decimal (two’s complement)
2047
Temperature in °C(*) 127.9375
0110’1001’0000
690
1680
1680
105
0101’0101’0000
550
1360
1360
85
0100’1011’0000
4B0
1200
1200
75
0011’0010’0000
320
800
800
50
0001’1001’0000
190
400
400
25
0000’0001’0000
010
16
16
1
0000’0000’0100
004
4
4
0.25
0000’0000’0001
001
1
1
0.0625
0000’0000’0000 (default)
000
0
0
0
1111’1111’1111
FFF
4095
-1
-0.0625
1111’1111’1100
FFC
4092
-4
-0.25
1111’1111’0000
FF0
4080
-16
-1
1110’0111’0000
E70
3696
-400
-25
1101’1000’0000
D80
3456
-640
-40
1000’0000’0000
800
2048
-2048
-128
(*) Temperature value in °C = Signed decimal / 16 = Signed decimal × 0.0625. Note that there is no need to read the Temperature LSBs byte (TEMP [3:0]) if resolution below 1°C is not required. Note that the thermometer must not be operated outside the temperature range from -40 to +105°C specified by the RV-3032-C7 module.
Note: The Temperature LSBs and Temperature MSBs registers know no blocking/shadowing. To get a valid 12-bit temperature value, the TEMP [11:0] value should be read after the 1 Hz tick, or up to 1 ms before a 1 Hz tick (or TEMP [11:0] value can be read twice, and then compared).
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3.9. CONTROL REGISTERS
10h Control 1 This register is used to specify the source for the Periodic
Time Update Interrupt function and to select or set operations for the
Periodic Countdown Timer. It also holds the control bit for automatic refresh
of the Configuration Registers. Read: Always readable. Write: Can be write-
protected by password.
Address 10h Bit 7:6 5
4
3
2
1:0
TD value 00 01 10 11
Function Control 1 Reset
Conv. R/WP
Bit 7 0
Bit 6 0
Bit 5 GP0
0
Bit 4 USEL
0
Bit 3 TE 0
Bit 2 EERD
0
Bit 1
Bit 0
TD
0
0
Symbol GP0 USEL
TE
EERD
TD
Value
Description
0
Bit not implemented. Will return a 0 when read.
0 or 1 Register bit for general purpose use.
Update Interrupt Select bit. Specifies either Second or Minute update for the
Periodic Time Update Interrupt function.
(see PERIODIC TIME UPDATE INTERRUPT FUNCTION). When STOP bit is set to 1 the
interrupt function is stopped. When writing to the Seconds register or when
ESYN bit is 1 in case of an External Event detection on EVI
pin the length of the current update period is affected (see TIME
SYNCHRONIZATION).
0
Second update (Auto reset time tRTN2 = 500 ms). Default value
1
Minute update (Auto reset time tRTN2 = 15.6 ms).
Periodic Countdown Timer Enable bit. This bit controls the start/stop setting for the
Periodic Countdown Timer Interruption function
(see PERIODIC COUNTDOWN TIMER INTERRUPT FUNCTION).
0
Stops the Periodic Countdown Timer Interrupt function. Default value
1
Starts the Periodic Countdown Timer Interrupt function (a countdown starts from the preset value set in Timer Value registers).
EEPROM Memory Refresh Disable bit. When 1, disables the automatic refresh of the
Configuration Registers from the EEPROM Memory (see AUTOMATIC REFRESH (ALL CONFIGURATION EEPROM RAM)).
Refresh is active. All data in the Configuration Registers are refreshed by
the data stored in the EEPROM each 24 hours, at date increment (at the
0
beginning of the last second before midnight). The time of this automatic
refreshment is tAREFR = ~3.5 ms. Refresh is only active when RTC is not in VBACKUP Power state and VDD VLOW. Default value
1
Refresh is disabled.
00 to 11
Timer Clock Frequency selection. Sets the countdown source clock for the Periodic Countdown Timer Interrupt function. With this setting the Auto reset time tRTN1 is also defined. See table below (see also PERIODIC COUNTDOWN TIMER INTERRUPT FUNCTION). When the clock source has been set to Second update (1 Hz) or Minute update (1/60 Hz), the timing of both, countdown and interrupts, is coordinated with the clock update timing but has a maximum jitter of 30.5 µs. When STOP bit is set to 1 the interrupt function is stopped. When writing to the Seconds register or when ESYN bit is 1 in case of an External Event detection on EVI pin the length of the current countdown period is affected (see TIME SYNCHRONIZATION).
Timer Clock Frequency 4096 Hz Default value 64 Hz 1 Hz 1/60 Hz
Countdown period 244.14 s 15.625 ms 1 s 60 s
122 s
tRTN1
7.813 ms
STOP bit
When STOP bit is set to 1 the interrupt function is stopped (see also TIME
SYNCHRONIZATION).
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11h Control 2 This register is used to enable the interrupt controlled clock
output on CLKOUT pin and to control the interrupt event output for the INT pin
and the stop/start status of clock and calendar operations.
Read: Always readable. Write: Can be write-protected by password.
Address 11h
Function Control 2 Reset
Conv. R/WP
Bit 7 0
Bit 6 CLKIE
0
Bit 5 UIE
0
Bit 4 TIE
0
Bit 3 AIE
0
Bit 2 EIE
0
Bit 1 GP1
0
Bit 0 STOP
0
Bit
Symbol
Value
Description
7
–
0
Bit not implemented. Will return a 0 when read.
Interrupt Controlled Clock Output Enable bit. When enabled, it is possible to
wake-up an external system by outputting a frequency.
(see INTERRUPT CONTROLLED CLOCK OUTPUT)
6
CLKIE
5
UIE
4
TIE
3
AIE
2
EIE
0
Disabled Default value
When set to 1, the clock output on CLKOUT pin is automatically enabled
when an interrupt occurs, based on the Clock Interrupt Mask (register 14h)
1
and according to the clock setting defined in registers EEPROM Clkout 1
and EEPROM Clkout 2 (C2h and C3h).
This function is disabled in VBACKUP Power state.
Periodic Time Update Interrupt Enable bit
(see PERIODIC TIME UPDATE INTERRUPT FUNCTION)
No interrupt signal is generated on INT pin and UF flag is not set when a
0
Periodic Time Update event occurs or the tRTN2 – signal on INT pin is
cancelled. Default value An interrupt signal is generated on INT pin and the UF flag is set when a
1
Periodic Time Update event occurs. The low-level output signal is automatically cleared after tRTN2 = 500 ms (Second update) or
tRTN2 = 15.6 ms (Minute update). (1)
Periodic Countdown Timer Interrupt Enable bit
(see PERIODIC COUNTDOWN TIMER INTERRUPT FUNCTION)
No interrupt signal is generated on INT pin when a Periodic Countdown
0
Timer event occurs or the tRTN1 – signal on INT pin is cancelled.
Default value An interrupt signal is generated on INT pin when a Periodic Countdown
1
Timer event occurs. The low-level output signal is automatically cleared
after tRTN1 = 122 µs (TD = 00) or tRTN1 = 7.813 ms (TD = 01, 10, 11). (1)
Alarm Interrupt Enable bit (see ALARM INTERRUPT FUNCTION)
0
No interrupt signal is generated on INT pin when an Alarm event occurs or the signal is cancelled on INT pin. Default value
An interrupt signal is generated on INT pin when an Alarm event occurs.
1
The signal on INT pin is retained until the AF flag is cleared to 0 (no
automatic cancellation). (1)
External Event Interrupt Enable bit
(see EXTERNAL EVENT INTERRUPT FUNCTION and INTERRUPT SCHEME)
0
No interrupt signal is generated on INT pin when an External Event on EVI pin occurs or the signal is cancelled on INT pin. Default value
An interrupt signal is generated on INT pin when an External Event on EVI
1
pin occurs. The signal on INT pin is retained until the EVF flag is cleared to
0 (no automatic cancellation). (1)
1
GP1
0 or 1 Register bit for general purpose use.
Stop bit. This bit is used for a software-based time adjustment (synchronization) (see STOP BIT FUNCTION).
0
Not stopped. Default value
Stops and resets the clock prescaler frequencies from 4096 Hz to 1 Hz
and the 100th Seconds register is reset to 00.
0
STOP
A possible currently memorized 1 Hz update is also reset. The following functions are stopped: Clock and calendar (with alarm),
1
CLKOUT, timer clock, update timer clock, EVI input filter, temperature measurement, temperature compensation and temperature comparison
with THT and TLT values are stopped (see also TIME
SYNCHRONIZATION).
The External Event Interrupt function is still working but cannot provide
useful data.
(1) Interrupt Delay after CLKOUT On can be activated by setting bit INTDE.
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12h This
Control register is
3 used
to
enable
temperature
detections
and
to
control
the
interrupt
event
output
for
the
INT
pin.
Read: Always readable. Write: Can be write-protected by password.
Address 12h
Function Control 3 Reset
Conv. R/WP
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 BSIE
0
Bit 3 THE
0
Bit 2 TLE
0
Bit 1 THIE
0
Bit 0 TLIE
0
Bit
Symbol
Value
Description
7:5
–
0
Bit not implemented. Will return a 0 when read.
4
BSIE
Backup Switchover Interrupt Enable bit
(see AUTOMATIC BACKUP SWITCHOVER FUNCTION and
AUTOMATIC BACKUP SWITCHOVER INTERRUPT FUNCTION)
0
No interrupt signal is generated on INT pin when an Automatic Backup Switchover occurs or the signal is cancelled on INT pin. Default value
An interrupt signal is generated on INT pin when an Automatic Backup
1
Switchover occurs. The signal on INT pin is retained until the BSF flag is
cleared to 0 (no automatic cancellation).
Temperature High Enable bit (see TEMPERATURE HIGH INTERRUPT FUNCTION)
3
THE
0
Temperature High detection is disabled. Default value
Enables the Temperature High detection with programmable Temperature
1
High Threshold, and the corresponding Time Stamp function. An event is
generated every second, when TEMP [11:4] > THT.
Temperature Low Enable bit (see TEMPERATURE LOW INTERRUPT FUNCTION)
2
TLE
0
Temperature Low detection is disabled. Default value
Enables the Temperature Low detection with programmable Temperature
1
Low Threshold, and the corresponding Time Stamp function. An event is
generated every second, when TEMP [11:4] < TLT.
Temperature High Interrupt Enable bit
1
THIE
(see TEMPERATURE HIGH INTERRUPT FUNCTION and INTERRUPT SCHEME)
0
No interrupt signal is generated on INT pin when Temperature High is detected or the signal is cancelled on INT pin. Default value
An interrupt signal is generated on INT pin when Temperature High is
1
detected. The signal on INT pin is retained until the THF flag is cleared to 0
(no automatic cancellation). (1) (2)
Temperature Low Interrupt Enable bit
0
TLIE
(see TEMPERATURE LOW INTERRUPT FUNCTION and INTERRUPT SCHEME)
0
No interrupt signal is generated on INT pin when Temperature Low is detected or the signal is cancelled on INT pin. Default value
An interrupt signal is generated on INT pin when Temperature Low is
1
detected. The signal on INT pin is retained until the TLF flag is cleared to 0
(no automatic cancellation). (1) (2)
(1) Interrupt Delay after CLKOUT On can be activated by setting bit INTDE.
(2) Note that the THF and TLF flags are always reset whenever the register 0Dh Status is written to (using 0s or 1s).
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3.10. TIME STAMP CONTROL REGISTER
13h Time Stamp Control This register holds the control bits for the Time
Stamp data. Read: Always readable. Write: Can be write-protected by password.
Address 13h Bit 7:6
5
Function Time Stamp Control Reset
Symbol
EVR
4
THR
3
TLR
2
EVOW
1
THOW
0
TLOW
Conv. Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/WP
0
EVR
THR
TLR EVOW THOW TLOW
0
0
0
0
0
0
0
Value
Description
0
Read only. Always 0.
Time Stamp EVI Reset bit (see TIME STAMP EVI FUNCTION)
0
Disabled. Default value
Writing 1 to the EVR bit resets all eight Time Stamp EVI registers (TS EVI
1
Count to TS EVI Year) to 00h.
EVR may remain set. No further reset occurs.
Time Stamp THigh Reset bit (see TIME STAMP THIGH FUNCTION)
0
Disabled. Default value
Writing 1 to the THR bit resets all seven Time Stamp THigh registers (TS
1
THigh Count to TS THigh Year) to 00h and the THF flag is also cleared to
0. The THR bit always returns 0 when read.
Time Stamp TLow Reset bit (see TIME STAMP TLOW FUNCTION)
0
Disabled. Default value
Writing 1 to the TLR bit resets all seven Time Stamp TLow registers (TS
1
TLow Count to TS TLow Year) to 00h and the TLF flag is also cleared to 0.
The TLR bit always returns 0 when read.
Time Stamp EVI Overwrite bit. Controls the overwrite function of the TS EVI registers (TS EVI 100th Seconds to TS EVI Year). The TS EVI Count register always counts
events, regardless of the settings of the override bit EVOW.
(see TIME STAMP EVI FUNCTION)
The time stamp of the first occurred event is recorded and remains in TS
EVI registers. Default value To initialize or reinitialize the first event detection function, 1 has to be
written to the EVR bit to clear all TS EVI registers (POR has same effect,
0
when EVI pin = HIGH).
Caution: For the Time Stamp EVI function, only the TS EVI Count register
is responsible for detecting first or last event, and therefore, always after
an overflow of the TS EVI Count register from 255 to 0, a new First Event
is allowed by the function (see also TIME STAMP EVI SCHEME).
1
The time stamp of the last occurred event is recorded and TS EVI registers are overwritten.
Time Stamp THigh Overwrite bit. Controls the overwrite function of the TS THigh
registers (TS THigh Seconds to TS THigh Year). The TS THigh Count register always
counts events, regardless of the settings of the override bit THOW.
(see TIME STAMP THIGH FUNCTION)
The time stamp of the first occurred event is recorded and remains in TS
THigh registers. Default value
0
To initialize or reinitialize the first event detection function, 1 has to be
written to the THR bit to clear all TS THigh registers (POR has same
effect).
1
The time stamp of the last occurred event is recorded and TS THigh registers are overwritten.
Time Stamp TLow Overwrite bit. Controls the overwrite function of the TS TLow
registers (TS TLow Seconds to TS TLow Year). The TS TLow Count register always
counts events, regardless of the settings of the override bit TLOW.
(see TIME STAMP TLOW FUNCTION)
The time stamp of the first occurred event is recorded and remains in TS
0
TLow registers. Default value To initialize or reinitialize the first event detection function, 1 has to be
written to the TLR bit clear all TS TLow registers (POR has same effect).
1
The time stamp of the last occurred event is recorded and TS TLow registers are overwritten.
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3.11. CLOCK INTERRUPT MASK REGISTER
14h Clock Interrupt Mask This register is used select a CLKOUT off Delay
Value after I2C STOP and to enable the Interrupt Delay after CLKOUT On. It is
also used to select a predefined interrupt for Interrupt Controlled Clock
Output. Setting a bit to 1 selects the corresponding interrupt. Multiple
interrupts can be selected. After power on, no interrupt is selected (see
INTERRUPT SCHEME and CLOCK OUTPUT SCHEME). Read: Always readable. Write: Can
be write-protected by password.
Address 14h
Function
Clock Interrupt Mask Reset
Conv. R/WP
Bit 7 CLKD
0
Bit 6 INTDE
0
Bit 5 CEIE
0
Bit 4 CAIE
0
Bit 3 CTIE
0
Bit 2 CUIE
0
Bit 1 CTHIE
0
Bit 0 CTLIE
0
Bit
Symbol
Value
Description
7
CLKD
CLKOUT (switch) off Delay Value after I2C STOP Selection bit.
Applicable only when CLKDE bit in the EVI Control register is set to 1.
(see CLKOUT OFF DELAY AFTER I2C STOP)
0
Typical delay time tI2C:CLK = 1.4 ms. Default value
6
INTDE
1
Typical delay time tI2C:CLK = 75 ms.
Interrupt Delay after CLKOUT On Enable bit.
Applicable only when NCLKE bit in the EEPROM PMU register is set to 1 (CLKOUT
not directly enabled) and for interrupts enabled by CEIE, CAIE, CTIE, CUIE, CTHIE or
CTLIE (see INTERRUPT DELAY AFTER CLKOUT ON)
0
No delay. Default value
1
Enables the delay time tCLK:INT of 1/256 seconds to 3/512 seconds 3.9 ms to 5.9 ms.
Clock output when EVI Interrupt Enable bit.
5
CEIE
0
Disabled Default value
1
Enabled. Internal signal EI is selected. (1)
Clock output when Alarm Interrupt Enable bit.
4
CAIE
0
Disabled Default value
1
Enabled. Internal signal AI is selected. (1)
Clock output when Periodic Countdown Timer Interrupt Enable bit.
3
CTIE
0
Disabled Default value
1
Enabled: Internal signal TI is selected. (1) If TD = 00 (4096 Hz) is selected, no interrupt delay is added.
Clock output when Periodic Time Update Interrupt Enable bit.
2
CUIE
0
Disabled Default value
1
Enabled. Internal signal UI is selected. (1)
Clock output when THigh Interrupt Enable bit.
1
CTHIE
0
Disabled Default value
1
Enabled. Internal signal THI is selected. (1)
Clock output when TLow Interrupt Enable bit
0
CTLIE
0
Disabled Default value
1
Enabled. Internal signal TLI is selected. (1)
(1) Interrupt Delay after CLKOUT On can be activated by setting bit INTDE.
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3.12. EVI CONTROL REGISTER
15h EVI Control This register controls the event detection on the EVI pin.
Depending of the EHL bit, high or low level (or rising or falling edge) can be
detected. Moreover a digital glitch filtering can be applied to the EVI signal
by selecting a sampling period tSP in the ET field. Furthermore this register
holds the enable bit for the CLKOUT off Delay after I2C STOP and the External
Event Synchronization bit. Read: Always readable. Write: Can be write-
protected by password.
Address 15h Bit
7
Function EVI Control Reset Symbol
CLKDE
6
EHL
5:4
ET
3:1
0
ESYN
Conv. R/WP
Bit 7 CLKDE
0
Bit 6 EHL
0
Bit 5
Bit 4
ET
0
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0 ESYN
0
Value
Description
CLKOUT (switch) off Delay after I2C STOP Enable bit
0
Disabled Default value
1
Enabled. The delay time tI2C:CLK can be selected with CLKD bit in Clock Interrupt Mask register.
Event High/Low Level (Rising/Falling Edge) selection for detection
(see EXTERNAL EVENT INTERRUPT FUNCTION)
0
The falling edge (ET = 00) or low level (ET 00) is regarded as the External Event on pin EVI. Default value
1
The rising edge (ET = 00) or high level (ET 00) is regarded as the External Event on pin EVI.
Event Filtering Time set.
Applies a digital filtering to the EVI pin by sampling the EVI signal.
(see EXTERNAL EVENT INTERRUPT FUNCTION).
00
No filtering. Edge detection. Default value
01
Sampling period tSP = 3.9 ms (256 Hz). Edge & Level detection.
10
Sampling period tSP = 15.6 ms (64 Hz). Edge & Level detection.
11
Sampling period tSP = 125 ms (8 Hz). Edge & Level detection.
0
Read only. Always 0.
External Event (EVI) Synchronization bit. This bit is used for a hardware- based time adjustment (see ESYN BIT FUNCTION).
0
Disabled Default value
In case of an External Event detection at the EVI pin the clock prescaler
frequencies from 4096 Hz to 1 Hz are reset and the 100th Seconds register
is reset to 00. A possible currently memorized 1 Hz update is also reset.
1
When an External Event occurs, the Time Stamp EVI is always created first and then the 100th Seconds register is cleared to 00.
After the event detection, the ESYN bit is reset to 0 automatically.
If 1, the synchronization function can be canceled by resetting the ESYN
bit to 0 before an event occurs.
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3.13. TEMPERATURE THRESHOLDS REGISTERS
16h TLow Threshold In this register, the user can define the Temperature Low
Threshold value TLT which is compared with the TEMP [11:4] value in the
Temperature MSBs register. TLT is stored in the same two’s complement format
as the TEMP [11:4] (see TEMPERATURE REGISTERS). Read: Always readable. Write:
Can be write-protected by password.
Address 16h Bit
7:0
Function TLow Threshold Reset Symbol
TLT
Conv. R/WP
Bit 7
0 Value
-128 to 127
Bit 6 0
Bit 5 0
Bit 4
Bit 3
TLT
0
0
Bit 2 0
Bit 1 0
Bit 0 0
Description
Temperature Low Threshold value with 1°C resolution in two’s complement format
like TEMP [11:4]. The integer part TEMP [11:4] from the internal temperature
is automatically compared to this value. An event is generated when TEMP
[11:4] < TLT (see TEMPERATURE REGISTERS, TEMPERATURE LOW INTERRUPT FUNCTION
and TIME STAMP TLOW FUNCTION).
17h THigh Threshold In this register, the user can define the Temperature
High Threshold value THT which is compared with the TEMP
[11:4] value in the Temperature MSBs register. THT is stored in the same two’s
complement format as the TEMP [11:4] (see TEMPERATURE REGISTERS).
Read: Always readable. Write: Can be write-protected by password.
Address 17h Bit
7:0
Function THigh Threshold Reset Symbol
THT
Conv. R/WP
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4
Bit 3
THT
0
0
Bit 2 0
Bit 1 0
Bit 0 0
Value
-128 to 127
Description
Temperature High Threshold value with 1°C resolution in two’s complement
format like TEMP [11:4]. The integer part TEMP [11:4] from the internal
temperature is automatically compared to this value. An event is generated
when TEMP [11:4] > THT (see TEMPERATURE REGISTERS, TEMPERATURE HIGH INTERRUPT
FUNCTION and TIME STAMP THIGH FUNCTION).
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3.14. TIME STAMP TLOW REGISTERS
Seven Time Stamp TLow registers (TS TLow Count and TS TLow Seconds to TS TLow
Year), (see TIME STAMP TLOW FUNCTION).
18h TS TLow Count This register contains the number of occurrences of
Temperature Low events (TEMP [11:4] < TLT) in standard binary format. The
values range from 0 to 255. Read only. Writing to this register has no effect.
Address 18h Bit
7:0
Function TS TLow Count Reset Symbol
TS TLow Count
Conv. R
Bit 7 128
0
Bit 6 64 0
Bit 5 32 0
Bit 4 16 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value 0 to 255
Description
Number of occurrences of Temperature Low events, coded in binary. In case of
an overflow the counter starts again with 00h. When bit TLE = 0, the counter
stops counting events. When bit TLE = 1, the counter is increased when event
occurs. The TS TLow Count register always counts events, regardless of the
settings of the override bit TLOW. The TS TLow Count register is reset to 00h
when 1 is written to the Time Stamp TLow Reset bit TLR (see TIME STAMP TLOW
FUNCTION).
19h TS TLow Seconds This register holds a recorded Temperature Low Time
Stamp of the Seconds register, in two binary coded decimal
(BCD) digits. The values are from 00 to 59.
Read only. Writing to this register has no effect.
Address 19h Bit 7
6:0
Function TS TLow Seconds Reset
Conv. R
Bit 7
0
Bit 6 40 0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Symbol
TS TLow Seconds
Value 0
00 to 59
Description
Read only. Always 0.
Holds a recorded Temperature Low Time Stamp of the Seconds register, coded in
BCD format. When enabled (bit TLE = 1), depending on the setting of the TLOW
bit, it contains the time stamp of the first or last occurred event. The TS
TLow Seconds register is reset to 00h when 1 is written to the Time Stamp TLow
Reset bit TLR (see TIME STAMP TLOW FUNCTION).
1Ah TS TLow Minutes This register holds a recorded Temperature Low Time
Stamp of the Minutes register, in two binary coded decimal
(BCD) digits. The values are from 00 to 59.
Read only. Writing to this register has no effect.
Address 1Ah Bit 7
6:0
Function TS TLow Minutes Reset Symbol
TS TLow Minutes
Conv. R
Bit 7
0
Bit 6 40 0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value 0
00 to 59
Description
Read only. Always 0.
Holds a recorded Temperature Low Time Stamp of the Minutes register, coded in
BCD format. When enabled (bit TLE = 1), depending on the setting of the TLOW
bit, it contains the time stamp of the first or last occurred event. The TS
TLow Minutes register is reset to 00h when 1 is written to the Time Stamp TLow
Reset bit TLR (see TIME STAMP TLOW FUNCTION).
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1Bh TS TLow Hours This register holds a recorded Temperature Low Time Stamp
of the Hours register, in two binary coded decimal
(BCD) digits. Values will range from 00 to 23.
Read only. Writing to this register has no effect.
Address 1Bh Bit 7:6
5:0
Function TS TLow Hours Reset Symbol
TS TLow Hours
Conv. R
Bit 7
0
Bit 6
0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value 0
00 to 23
Description
Read only. Always 0.
Holds a recorded Temperature Low Time Stamp of the Hours register, coded in
BCD format. When enabled (bit TLE = 1), depending on the setting of the TLOW
bit, it contains the time stamp of the first or last occurred event. The TS
TLow Hours register is reset to 00h when 1 is written to the Time Stamp TLow
Reset bit TLR (see TIME STAMP TLOW FUNCTION).
1Ch TS TLow Date This register holds a recorded Temperature Low Time Stamp
of the Date register, in two binary coded decimal (BCD)
digits. The values will range from 01 to 31.
Read only. Writing to this register has no effect.
Address 1Ch Bit 7:6
5:0
Function TS TLow Date Reset Symbol
TS TLow Date
Conv. R
Bit 7
0
Bit 6
0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value 0
01 to 31
Description
Read only. Always 0.
Holds a recorded Temperature Low Time Stamp of the Date register, coded in BCD
format. When enabled (bit TLE = 1), depending on the setting of the TLOW bit,
it contains the time stamp of the first or last occurred event. The TS TLow
Date register is reset to 00h when 1 is written to the Time Stamp TLow Reset
bit TLR (see TIME STAMP TLOW FUNCTION). The value 00 after POR or after the
reset with the TLR bit, is replaced by a valid value (01 to 31) when a
Temperature Low Time Stamp is recorded.
1Dh TS TLow Month This register holds a recorded Temperature Low Time Stamp
of the Month register, in two binary coded decimal
(BCD) digits. The values will range from 01 to 12.
Read only. Writing to this register has no effect.
Address 1Dh Bit 7:5
4:0
Function TS TLow Month Reset Symbol
TS TLow Month
Conv. R
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value 0
01 to 12
Description
Read only. Always 0.
Holds a recorded Temperature Low Time Stamp of the Month register, coded in
BCD format. When enabled (bit TLE = 1), depending on the setting of the TLOW
bit, it contains the time stamp of the first or last occurred event. The TS
TLow Month register is reset to 00h when 1 is written to the Time Stamp TLow
Reset bit TLR (see TIME STAMP TLOW FUNCTION). The value 00 after POR or after
the reset with the TLR bit, is replaced by a valid value (01 to 12) when a
Temperature Low Time Stamp is recorded.
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1Eh TS TLow Year This register holds a recorded Temperature Low Time Stamp
of the Year register, in two binary coded decimal (BCD)
digits. Values will range from 00 to 99.
Read only. Writing to this register has no effect.
Address 1Eh Bit
7:0
Function TS TLow Year Reset Symbol
TS TLow Year
Conv. R
Bit 7 80 0
Bit 6 40 0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value 00 to 99
Description
Holds a recorded Temperature Low Time Stamp of the Year register, coded in BCD
format. When enabled (bit TLE = 1), depending on the setting of the TLOW bit,
it contains the time stamp of the first or last occurred event. The TS TLow
Year register is reset to 00h when 1 is written to the Time Stamp TLow Reset
bit TLR (see TIME STAMP TLOW FUNCTION).
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3.15. TIME STAMP THIGH REGISTERS
Seven Time Stamp THigh registers (TS THigh Count and TS THigh Seconds to TS
THigh Year), (see TIME STAMP THIGH FUNCTION).
1Fh TS THigh Count This register contains the number of occurrences of
Temperature High events (TEMP [11:4] > THT) in standard binary format. The
values range from 0 to 255. Read only. Writing to this register has no effect.
Address 1Fh Bit
7:0
Function TS THigh Count Reset Symbol
TS THigh Count
Conv. R
Bit 7 128
0
Bit 6 64 0
Bit 5 32 0
Bit 4 16 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value 0 to 255
Description
Number of occurrences of Temperature High events, coded in binary. In case of
an overflow the counter starts again with 00h. When bit THE = 0, the counter
stops counting events. When bit THE = 1, the counter is increased when event
occurs. The TS THigh Count register always counts events, regardless of the
settings of the override bit THOW. The TS THigh Count register is reset to 00h
when 1 is written to the Time Stamp THigh Reset bit THR (see TIME STAMP THIGH
FUNCTION).
20h TS THigh Seconds This register holds a recorded Temperature High Time
Stamp of the Seconds register, in two binary coded decimal
(BCD) digits. The values are from 00 to 59.
Read only. Writing to this register has no effect.
Address 20h Bit 7
6:0
Function TS THigh Seconds Reset
Conv. R
Bit 7
0
Bit 6 40 0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Symbol
TS THigh Seconds
Value 0
00 to 59
Description
Read only. Always 0.
Holds a recorded Temperature High Time Stamp of the Seconds register, coded in
BCD format. When enabled (bit THE = 1), depending on the setting of the THOW
bit, it contains the time stamp of the first or last occurred event. The TS
THigh Seconds register is reset to 00h when 1 is written to the Time Stamp
THigh Reset bit THR (see TIME STAMP THIGH FUNCTION).
21h TS THigh Minutes This register holds a recorded Temperature High Time
Stamp of the Minutes register, in two binary coded decimal
(BCD) digits. The values are from 00 to 59.
Read only. Writing to this register has no effect.
Address 21h Bit 7
6:0
Function TS THigh Minutes Reset
Conv. R
Bit 7
0
Bit 6 40 0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Symbol
TS THigh Minutes
Value 0
00 to 59
Description
Read only. Always 0.
Holds a recorded Temperature High Time Stamp of the Minutes register, coded in
BCD format. When enabled (bit THE = 1), depending on the setting of the THOW
bit, it contains the time stamp of the first or last occurred event. The TS
THigh Minutes register is reset to 00h when 1 is written to the Time Stamp
THigh Reset bit THR (see TIME STAMP THIGH FUNCTION).
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22h TS THigh Hours This register holds a recorded Temperature High Time
Stamp of the Hours register, in two binary coded decimal
(BCD) digits. Values will range from 00 to 23.
Read only. Writing to this register has no effect.
Address 22h Bit 7:6
5:0
Function TS THigh Hours Reset Symbol
TS THigh Hours
Conv. R
Bit 7
0
Bit 6
0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value 0
00 to 23
Description
Read only. Always 0.
Holds a recorded Temperature High Time Stamp of the Hours register, coded in
BCD format. When enabled (bit THE = 1), depending on the setting of the THOW
bit, it contains the time stamp of the first or last occurred event. The TS
THigh Hours register is reset to 00h when 1 is written to the Time Stamp THigh
Reset bit THR (see TIME STAMP THIGH FUNCTION).
23h TS THigh Date This register holds a recorded Temperature High Time Stamp
of the Date register, in two binary coded decimal (BCD)
digits. The values will range from 01 to 31.
Read only. Writing to this register has no effect.
Address 23h Bit 7:6
5:0
Function TS THigh Date Reset Symbol
TS THigh Date
Conv. R
Bit 7
0
Bit 6
0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value 0
01 to 31
Description
Read only. Always 0.
Holds a recorded Temperature High Time Stamp of the Date register, coded in
BCD format. When enabled (bit THE = 1), depending on the setting of the THOW
bit, it contains the time stamp of the first or last occurred event. The TS
THigh Date register is reset to 00h when 1 is written to the Time Stamp THigh
Reset bit THR (see TIME STAMP THIGH FUNCTION). The value 00 after POR or after
the reset with the THR bit, is replaced by a valid value (01 to 31) when a
Temperature High Time Stamp is recorded.
24h TS THigh Month This register holds a recorded Temperature High Time
Stamp of the Month register, in two binary coded decimal
(BCD) digits. The values will range from 01 to 12.
Read only. Writing to this register has no effect.
Address 24h Bit 7:5
4:0
Function TS THigh Month Reset Symbol
TS THigh Month
Conv. R
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value 0
01 to 12
Description
Read only. Always 0.
Holds a recorded Temperature High Time Stamp of the Month register, coded in
BCD format. When enabled (bit THE = 1), depending on the setting of the THOW
bit, it contains the time stamp of the first or last occurred event. The TS
THigh Month register is reset to 00h when 1 is written to the Time Stamp THigh
Reset bit THR (see TIME STAMP THIGH FUNCTION). The value 00 after POR or after
the reset with the THR bit, is replaced by a valid value (01 to 12) when a
Temperature Low Time Stamp is recorded.
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25h TS THigh Year This register holds a recorded Temperature High Time Stamp
of the Year register, in two binary coded decimal (BCD)
digits. Values will range from 00 to 99.
Read only. Writing to this register has no effect.
Address 25h Bit
7:0
Function TS THigh Year Reset Symbol
TS THigh Year
Conv. R
Bit 7 80 0
Bit 6 40 0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value 00 to 99
Description
Holds a recorded Temperature High Time Stamp of the Year register, coded in
BCD format. When enabled (bit THE = 1), depending on the setting of the THOW
bit, it contains the time stamp of the first or last occurred event. The TS
THigh Year register is reset to 00h when 1 is written to the Time Stamp THigh
Reset bit THR (see TIME STAMP THIGH FUNCTION).
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3.16. TIME STAMP EVI REGISTERS
Eight Time Stamp EVI registers (TS EVI Count and TS EVI 100th Seconds to TS
EVI Year), (see TIME STAMP EVI FUNCTION).
26h TS EVI Count This register contains the number of occurrences of
External Events on EVI pin in standard binary format. The values range from 0
to 255. Read only. Writing to this register has no effect.
Address 26h Bit
7:0
Function TS EVI Count Reset Symbol
TS EVI Count
Conv. R
Bit 7 128
0
Bit 6 64 0
Bit 5 32 0
Bit 4 16 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 X
Value 0 to 255
Description
Number of occurrences of External Events on EVI pin, coded in binary. In case
of an overflow the counter starts again with 00h. The TS EVI Count register
always counts events, regardless of the settings of the override bit EVOW. The
TS EVI Count register is reset to 00h when 1 is written to the Time Stamp EVI
Reset bit EVR (see TIME STAMP EVI FUNCTION).
The Reset value X depends on the voltage on the EVI pin at POR. Because EHL =
0 at POR, the low level is regarded as an External Event Interrupt. If X = 1,
a LOW level was detected on EVI pin. If X = 0, no LOW level was detected on
EVI pin.
27h TS EVI 100th Seconds This register holds a recorded External Event Time Stamp of the 100th Seconds register, in two binary coded decimal (BCD) digits. The values are from 00 to 99. Read only. Writing to this register has no effect.
Address 27h Bit
7:0
Function
TS EVI 100th Seconds Reset
Conv. R
Bit 7 80 0
Bit 6 40 0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Symbol TS EVI 100th Seconds
Value 00 to 99
Description
Holds a recorded External Event Time Stamp of the 100th Seconds register,
coded in BCD format. Depending on the setting of the EVOW bit, it contains the
time stamp of the first or last occurred event. The TS EVI 100th Seconds
register is reset to 00h when 1 is written to the Time Stamp EVI Reset bit EVR
(see TIME STAMP EVI FUNCTION).
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28h TS EVI Seconds This register holds a recorded External Event Time Stamp
of the Seconds register, in two binary coded decimal
(BCD) digits. The values are from 00 to 59.
Read only. Writing to this register has no effect.
Address 28h Bit 7
6:0
Function TS EVI Seconds Reset Symbol
TS EVI Seconds
Conv. R
Bit 7
0
Bit 6 40 0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value 0
00 to 59
Description
Read only. Always 0.
Holds a recorded External Event Time Stamp of the Seconds register, coded in
BCD format. Depending on the setting of the EVOW bit, it contains the time
stamp of the first or last occurred event. The TS EVI Seconds register is
reset to 00h when 1 is written to the Time Stamp EVI Reset bit EVR (see TIME
STAMP EVI FUNCTION).
29h TS EVI Minutes This register holds a recorded External Event Time Stamp
of the Minutes register, in two binary coded decimal (BCD)
digits. The values are from 00 to 59.
Read only. Writing to this register has no effect.
Address 29h Bit 7
6:0
Function TS EVI Minutes Reset Symbol
TS EVI Minutes
Conv. R
Bit 7
0
Bit 6 40 0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value 0
00 to 59
Description
Read only. Always 0.
Holds a recorded External Event Time Stamp of the Minutes register, coded in
BCD format. Depending on the setting of the EVOW bit, it contains the time
stamp of the first or last occurred event. The TS EVI Minutes register is
reset to 00h when 1 is written to the Time Stamp EVI Reset bit EVR (see TIME
STAMP EVI FUNCTION).
2Ah TS EVI Hours This register holds a recorded External Event Time Stamp of
the Hours register, in two binary coded decimal (BCD)
digits. Values will range from 00 to 23.
Read only. Writing to this register has no effect.
Address 2Ah Bit 7:6
5:0
Function TS EVI Hours Reset Symbol
TS EVI Hours
Conv. R
Bit 7 0
Value 0
0 to 23
Bit 6
0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Description
Read only. Always 0.
Holds a recorded External Event Time Stamp of the Hours register, coded in BCD
format. Depending on the setting of the EVOW bit, it contains the time stamp
of the first or last occurred event. The TS EVI Hours register is reset to 00h
when 1 is written to the Time Stamp EVI Reset bit EVR (see TIME STAMP EVI
FUNCTION).
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2Bh TS EVI Date This register holds a recorded External Event Time Stamp of
the Date register, in two binary coded decimal (BCD)
digits. The values will range from 01 to 31.
Read only. Writing to this register has no effect.
Address 2Bh
Bit 7:6
Function TS EVI Date Reset
Symbol
5:0
TS EVI Date
Conv. R
Bit 7
0
Bit 6
0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 X
Value 0
Description
Read only. Always 0.
Holds a recorded External Event Time Stamp of the Date register, coded in BCD
format. Depending on the setting of the EVOW bit, it contains the time stamp
of the first or last occurred event. The TS EVI Date register is reset to 00h
when 1 is written to the Time Stamp EVI Reset bit EVR (see TIME STAMP EVI
FUNCTION).
01 to 31
The Reset value X depends on the voltage on the EVI pin at POR. Because EHL = 0 at POR, the low level is regarded as an External Event Interrupt and an External Event Time Stamp is recorded. If X = 1, a LOW level was detected on EVI pin. If X = 0, no LOW level was detected on EVI pin.
The value 00 after POR (if EVI-Pin = HIGH), or after the reset with the EVR bit, is replaced by a valid value (01 to 31) when an External Event Time Stamp is recorded.
2Ch TS EVI Month This register holds a recorded External Event Time Stamp of
the Month register, in two binary coded decimal (BCD)
digits. The values will range from 01 to 12.
Read only. Writing to this register has no effect.
Address 2Ch Bit 7:5
4:0
Function TS EVI Month Reset Symbol
TS EVI Month
Conv. R
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 X
Value 0
Description
Read only. Always 0.
Holds a recorded External Event Time Stamp of the Month register, coded in BCD
format. Depending on the setting of the EVOW bit, it contains the time stamp
of the first or last occurred event. The TS EVI Month register is reset to 00h
when 1 is written to the Time Stamp EVI Reset bit EVR (see TIME STAMP EVI
FUNCTION).
01 to 12
The Reset value X depends on the voltage on the EVI pin at POR. Because EHL = 0 at POR, the low level is regarded as an External Event Interrupt and an External Event Time Stamp is recorded. If X = 1, a LOW level was detected on EVI pin. If X = 0, no LOW level was detected on EVI pin.
The value 00 after POR (if EVI-Pin = HIGH), or after the reset with the EVR bit, is replaced by a valid value (01 to 12) when an External Event Time Stamp is recorded.
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2Dh TS EVI Year This register holds a recorded External Event Time Stamp of
the Year register, in two binary coded decimal (BCD)
digits. Values will range from 00 to 99.
Read only. Writing to this register has no effect.
Address 2Dh Bit
7:0
Function TS EVI Year Reset Symbol
TS EVI Year
Conv. R
Bit 7 80 0
Bit 6 40 0
Bit 5 20 0
Bit 4 10 0
Bit 3 8 0
Bit 2 4 0
Bit 1 2 0
Bit 0 1 0
Value 00 to 99
Description
Holds a recorded External Event Time Stamp of the Year register, coded in BCD
format. Depending on the setting of the EVOW bit, it contains the time stamp
of the first or last occurred event. The TS EVI Year register is reset to 00h
when 1 is written to the Time Stamp EVI Reset bit EVR (see TIME STAMP EVI
FUNCTION).
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3.17. PASSWORD REGISTERS
After a Power up and the first refreshment time tPREFR = ~66 ms, the Password
PW registers are reset to 00h. When the password function is enabled (EEPWE =
255), the correct 32-Bit Password must be written to the Password PW registers
to write to the registers with the WP convention (time, control, user RAM,
configuration EEPROM and user EEPROM registers). The 32-Bit Password PW is
compared with the 32 bits in the RAM mirror of the EEPW registers (see EEPROM
PASSWORD REGISTERS).
39h Password 0 Bit 0 to 7 from 32-bit Password. Write only. Returns 0 when
read.
Address 39h
Bit 7:0
Function Password 0 Reset
Symbol PW [7:0]
3Ah Password 1 Bit 8 to 15 from 32-bit Password.
Write only. Returns 0 when read.
Conv. W
Bit 7
0 Value 00h to FFh
Bit 6 0
Bit 5 0
Bit 4
Bit 3
PW [7:0]
0
0
Bit 2 0
Description Bit 0 to 7 from 32-bit Password
Bit 1 0
Bit 0 0
Address 3Ah
Bit 7:0
Function Password 1 Reset
Symbol PW [15:8]
Conv. W
Bit 7
0 Value 00h to FFh
Bit 6 0
Bit 5 0
Bit 4
Bit 3
PW [15:8]
0
0
Bit 2 0
Description
Bit 8 to 15 from 32-bit Password
3Bh Password 2 Bit 16 to 23 from 32-bit Password.
Write only. Returns 0 when read.
Bit 1 0
Bit 0 0
Address 3Bh
Bit 7:0
Function Password 2 Reset
Symbol PW [23:16]
Conv. W
Bit 7
0 Value 00h to FFh
Bit 6 0
Bit 5 0
Bit 4
Bit 3
PW [23:16]
0
0
Bit 2 0
Description Bit 16 to 23 from 32-bit Password
3Ch Password 3 Bit 24 to 31 from 32-bit Password.
Write only. Returns 0 when read.
Bit 1 0
Bit 0 0
Address 3Ch
Bit 7:0
Function Password 3 Reset
Symbol PW [31:24]
Conv. W
Bit 7
0
Value 00h to FFh
Bit 6 0
Bit 5 0
Bit 4
Bit 3
PW [31:24]
0
0
Bit 2 0
Description Bit 24 to 31 from 32-bit Password
Bit 1 0
Bit 0 0
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3.18. EEPROM MEMORY CONTROL REGISTERS
See also EEPROM READ/WRITE.
3Dh EE Address This register holds the Address used for read or write
from/to a single EEPROM Memory byte. Read: Always readable. Write: Can be
write-protected by password.
Address 3Dh Bit 7:0
Function EE Address Reset Symbol
EEADDR
Conv. R/WP
Bit 7
1 Value 00h to FFh
Bit 6 1
Bit 5 0
Bit 4
Bit 3
EEADDR
0
0
Bit 2 0
Bit 1 0
Bit 0 0
Description
Address for direct read or write one EEPROM Memory byte. Default value = C0h
The default address C0h points to the first Configuration EEPROM Register
(EEPROM PMU)
3Eh EE Data This register holds the Data that are read from, or that are
written to a single EEPROM Memory byte.
Read: Always readable. Write: Can be write-protected by password.
Address 3Eh
Bit 7:0
Function EE Data Reset
Symbol EEDATA
Conv. R/WP
Bit 7
0 Value 00h to FFh
Bit 6 0
Bit 5 0
Bit 4
Bit 3
EEDATA
0
0
Bit 2 0
Bit 1 0
Bit 0 0
Description
Data from direct read or for direct write to one EEPROM Memory byte. Default
value = 00h
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3Fh EE Command This register must be written with specific values, in order to Update or Refresh all (readable/writeable) Configuration EEPROM registers or to read or write from/to a single EEPROM Memory byte. Before using this commands, the automatic refresh function has to be disabled (EERD = 1) and the busy status bit EEbusy has to indicate that the last transfer has been finished (EEbusy = 0). The EEF flag can be used for EEPROM write access failure detection. Other values, unless 11h, 12h, 21h or 22h, should not be entered. Write only. Returns 0 when read. Can be write-protected by password.
Address 3Fh Bit
7:0
Function EE Command Reset Symbol
EECMD
Conv. WP
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4
Bit 3
EECMD
0
0
Bit 2 0
Bit 1 0
Bit 0 0
Value 11h 12h 21h 22h
Description
Commands for EEPROM Memory (see EEPROM READ/WRITE) Other values, unless 11h,
12h, 21h or 22h, should not be entered. UPDATE (ALL CONFIGURATION RAM EEPROM).
When writing a value of 11h, data from all Configuration RAM mirror bytes
(address C0h to CAh) are written (stored) into the corresponding Configuration
EEPROM bytes. See also USE OF THE CONFIGURATION REGISTERS. REFRESH (ALL
CONFIGURATION EEPROM RAM). When writing a value of 12h, data from all
Configuration EEPROM bytes are read and copied into the corresponding
Configuration RAM mirror bytes (address C0h to CAh). Functions become active
as soon as the RAM bytes are written. WRITE TO ONE EEPROM BYTE (EEDATA (RAM)
EEPROM). When writing a value of 21h, data from the EEDATA (RAM) byte are
written (stored) into the EEPROM byte with the address specified in the EEADDR
byte. For Configuration EEPROM bytes (address C0h to CAh) and User EEPROM
bytes (address CBh to EAh). READ ONE EEPROM BYTE (EEPROM EEDATA (RAM)). When
writing a value of 22h, data from the EEPROM byte with the address specified
in EEADDR byte are read and copied into the EEDATA (RAM) byte. For
Configuration EEPROM bytes (address C0h to CAh) and User EEPROM bytes (address
CBh to EAh).
3.19. RAM REGISTERS
40h to 4Fh User RAM 16 Bytes of User RAM for general purpose storage are
provided. For example, they can be used to store system status bytes. Read:
Always readable. Write: Can be write-protected by password.
Address 40h to 4Fh
Function User RAM
Conv. R/WP
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
16 Bytes of User RAM. Default values are 00h
Bit 0
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3.20. CONFIGURATION EEPROM WITH RAM MIRROR REGISTERS
All Configuration EEPROM registers at addresses C0h to CAh are memorized in
the EEPROM and mirrored in the RAM. Functions become active as soon as the RAM
mirror bytes are written. See also USE OF THE CONFIGURATION REGISTERS.
3.20.1. EEPROM PMU REGISTER
C0h EEPROM Power Management Unit (PMU) This register is used to control the
switchover function, the trickle charger with charge pump and it holds the
NCLKE bit (see PROGRAMMABLE CLOCK OUTPUT). After a Power up and the first
refreshment time tPREFR = ~66 ms, the EEPROM PMU register value is copied from
the EEPROM to the corresponding RAM mirror. The default value preset on
delivery is 00h. Read: Always readable. Write: Can be write-protected by
password.
Address C0h
Function
Conv.
EEPROM PMU
R/WP
Default value on delivery
Bit 7 0
Bit 6 NCLKE
0
Bit 5
Bit 4
BSM
0
0
Bit 3
Bit 2
TCR
0
0
Bit 1
Bit 0
TCM
0
0
Bit
Symbol
Value
Description
7
–
0
Bit not implemented. Will return a 0 when read.
6
NCLKE
Not CLKOUT Enable bit (see PROGRAMMABLE CLOCK OUTPUT)
(synchronized enable/disable)
0
CLKOUT is directly enabled. Default value on delivery
1
CLKOUT pin is LOW, if not enabled by the interrupt driven clock output (CLKF = 0) (see also INTERRUPT CONTROLLED CLOCK OUTPUT).
Backup Switchover Mode (see AUTOMATIC BACKUP SWITCHOVER FUNCTION, AUTOMATIC BACKUP SWITCHOVER INTERRUPT FUNCTION and
TRICKLE CHARGER WITH CHARGE PUMP)
To read/write from/to the EEPROM, the user has to disable the Backup Switchover
function by setting the BSM field to 00 or 11 (see routine in EEPROM READ/WRITE CONDITIONS)
5:4
BSM
00
Switchover Disabled. Default value on delivery
Enables the Direct Switching Mode (DSM).
01
Switchover when VDD < VBACKUP (PMU selects pin with the greater voltage
(VDD or VBACKUP)).
Enables the Level Switching Mode (LSM).
10
Switchover when VDD < VTH:LSM (2.0 V) AND VBACKUP > VTH:LSM (2.0 V).
When VDD < VTH:LSM (2.0 V), PMU is in DSM Mode.
11
Switchover Disabled.
Trickle Charger Series Resistance
(see TRICKLE CHARGER WITH CHARGE PUMP)
3:2
TCR
00
TCR 0.6 k Default value on delivery
01
TCR 2 k
10
TCR 7 k
11
TCR 12 k
Trickle Charger Mode (see TRICKLE CHARGER WITH CHARGE PUMP)
00
Trickle Charger off. Default value on delivery
TCM 1.75 V
01
In DSM Mode (BSM = 01), VDD voltage is selected. In LSM Mode (BSM = 10), the internal regulated voltage with the
1:0
TCM
typical value of 1.75 V is selected (CeraChargeTM mode). (1) TCM 3 V
10
In LSM Mode (BSM = 10), the internal charge pump voltage with
the typical value of 2.95 V is selected. (1)
TCM 4.4 V
11
In LSM Mode (BSM = 10), the internal charge pump voltage with
the typical value of 4.35 V is selected. (1)
(1) In LSM Mode (BSM = 10), the TCM voltage levels 1.75 V, 3 V or 4.4 V are only generated when VDD > VTH:LSM (maximum 2.2 V).
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3.20.2. EEPROM OFFSET REGISTER
C1h EEPROM Offset This register holds the OFFSET value for aging correction
of the frequency and the PORIE and VLIE bits to enable interrupt output. After
a Power up and the first refreshment time tPREFR = ~66 ms, the EEPROM Offset
register value is copied from the EEPROM to the corresponding RAM mirror. The
default value preset on delivery is 00h. Read: Always readable. Write: Can be
write-protected by password.
Address C1h
Function
Conv.
EEPROM Offset R/WP
Default value on delivery
Bit 7 PORIE
0
Bit 6 VLIE
0
Bit 5 0
Bit 4 0
Bit 3
Bit 2
OFFSET
0
0
Bit 1 0
Bit 0 0
Bit
Symbol
7
PORIE
6
VLIE
5:0
OFFSET
Value
0 1
0 1 -32 to +31
Description
Power On Reset Interrupt Enable bit (see POWER ON RESET INTERRUPT FUNCTION) No
interrupt signal is generated on INT pin when a Power On Reset occurs or the
signal is cancelled on INT pin. Default value on delivery An interrupt
signal is generated on INT pin when a Power On Reset occurs. This setting is
retained until the PORF flag is cleared to 0 (no automatic cancellation).
Voltage Low Interrupt Enable bit (see VOLTAGE LOW INTERRUPT FUNCTION) No
interrupt signal is generated on INT pin when a Voltage Low event occurs or
the signal is cancelled on INT pin. Default value on delivery An interrupt
signal is generated on INT pin when a Voltage Low event occurs. This setting
is retained until the VLF flag is cleared to 0 (no automatic cancellation).
The amount of the effective frequency offset. This is a two’s complement
number with a range of -32 to +31 adjustment steps (maximum correction range
is roughly ±7.4 ppm). The correction value of one LSB corresponds to
1/(32768*128) = 0.2384 ppm. Default value on delivery is 0 (see AGING
CORRECTION).
OFFSET 011111
Unsigned decimal 31
Signed decimal (two’s complement)
31
Offset value in ppm(*) 7.391
011110
30
30
7153
:
:
:
:
000001
1
1
0.238
000000 (default)
0
0
0.000
111111
63
-1
-0.238
111110
62
-2
-0.477
:
:
:
:
100001
33
-31
-7.391
100000
32
-32
-7.629
(*) Calculated with 5 decimal places (1/(32768 × 128) = 0.23842 ppm) The frequency deviation measured on the CLKOUT pin can be compensated by computing the OFFSET value and writing it into the EEPROM Offset register (see AGING CORRECTION).
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3.20.3. EEPROM CLKOUT REGISTERS
The registers EEPROM Clkout 1 and EEPROM Clkout 2 hold the values HFD [12:0],
OS and FD that define the frequency to be output. After a Power up and the
first refreshment time tPREFR = ~66 ms, the EEPROM Clkout 1 and EEPROM Clkout
2 values are copied from the EEPROM to the corresponding RAM mirror. The
programmable square wave output is available at CLKOUT pin. Operation can be
activated directly by setting NCLKE bit to 0 (EEPROM C0h) or by an interrupt
function (CLKF = 1) (see PROGRAMMABLE CLOCK OUTPUT).
C2h EEPROM Clkout 1 This register holds the lower 8 bits of the HFD value.
The default value preset on delivery is 00h (8192 Hz).
Read: Always readable. Write: Can be write-protected by password.
Address C2h
Bit 7:0
Function
Conv.
EEPROM Clkout 1
R/WP
Default value on delivery
Symbol HFD [7:0]
Bit 7
0 Value 00h to FFh
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HFD [7:0]
0
0
0
0
0
0
0
Description CLKOUT Frequency Selection in HF mode (lower 8 bits). See next table.
C3h EEPROM Clkout 2 This register holds the Oscillator Selection bit, the FD
value and the upper 5 bits of the HFD value. The default value
preset on delivery is 00h (XTAL selected, 32.768 kHz).
Read: Always readable. Write: Can be write-protected by password.
Address C3h
Function
Conv.
EEPROM Clkout 2
R/WP
Default value on delivery
Bit 7 OS 0
Bit 6
Bit 5
FD
0
0
Bit 4 0
Bit 3
Bit 2
Bit 1
HFD [12:8]
0
0
0
Bit 0 0
Bit
Symbol
7
OS
6:5
FD
4:0
HFD [12:8]
Value
0 1 00 to 11 00000 to 11111
Description Oscillator Selection (synchronized oscillator change) XTAL mode is
selected. Default value on delivery HF mode is selected. CLKOUT Frequency
Selection in XTAL mode. See table below.
CLKOUT Frequency Selection in HF mode (upper 5 bits). See next table.
FD value
CLKOUT Frequency Selection in XTAL mode
STOP bit
00
32.768 kHz Default value on delivery
No effect
01
1024 Hz (1) (2)
10
64 Hz (1) (2)
11
1 Hz (1) (2)
If STOP bit = 1, the clock output is stopped. CLKOUT remains HIGH or LOW. (3)
(1) 1024 Hz to 1 Hz clock pulses can be affected by compensation pulses (see TEMPERATURE COMPENSATION and
AGING CORRECTION). (2) Current period duration of 1024 Hz to 1 Hz clock pulses are affected when writing to the Seconds register or when the ESYN bit is 1 in
case of an External Event detection on EVI pin.
(3) 1024 Hz, 64 Hz and 1 Hz are synchronously turned on and off by the STOP bit.
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HFD (13 bits), 8.192 kHz to 67.109 MHz in 8.192 kHz steps:
HFD [12:0] value
HFD in decimal
HFD + 1
CLKOUT Frequency Selection in HF mode = (HFD + 1) × 8.192 kHz
STOP bit
0000000000000
0
1
8.192 kHz Default value on delivery
0000000000001
1
2
16.384 kHz
0000000000010
2
3
24.576 kHz
: 1100011001011
: 6347
6348
: 52.002816 MHz
No effect. (1) (2)
:
:
:
1111111111110
8190
8191
67.100672 MHz
1111111111111
8191
8192
67.108864 MHz
(1) Clock pulses from HF mode are not affected by compensation pulses (no
TEMPERATURE COMPENSATION and no AGING CORRECTION).
(2) Current period duration of clock pulses in HF mode are not affected when
writing to the Seconds register nor when the ESYN bit is 1 in case of an
External Event detection on EVI pin.
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3.20.4. EEPROM TEMPERATURE REFERENCE REGISTERS
The registers EEPROM TReference 0 and EEPROM TReference 1 hold the 16-bit
Temperature Reference value TREF in two’s complement format that is used to
calibrate the readable Temperature Value TEMP in registers 0Eh and 0Fh. TREF
defines the calibration steps that can be calculated. Each step introduces a
deviation of 0.0078125°C. The preconfigured (Factory Calibrated) TREF value
may be changed by the user (see TEMPERATURE REFERENCE ADJUSTMENT).
C4h EEPROM TReference 0 This register holds the lower 8 bits of the 16-bit
TREF value. The preconfigured (Factory Calibrated) TREF value may be changed
by the user. After a Power up and the first refreshment time tPREFR = ~66 ms,
the EEPROM
TReference 0 value is copied from the EEPROM to the corresponding RAM mirror.
Read: Always readable. Write: Can be write-protected by password.
Address C4h
Bit 7:0
Function
Conv.
EEPROM TReference 0
R/WP
Default value on delivery
Symbol TREF [7:0]
Bit 7
Value 00h to FFh
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
TREF [7:0] Preconfigured (Factory Calibrated)
Description Lower 8 bits of the TREF value.
Bit 1
Bit 0
C5h EEPROM TReference 1 This register holds the upper 8 bits of the 16-bit TREF value. The preconfigured (Factory Calibrated) TREF value may be changed by the user. After a Power up and the first refreshment time tPREFR = ~66 ms, the EEPROM TReference 1 value is copied from the EEPROM to the corresponding RAM mirror. Read: Always readable. Write: Can be write-protected by password.
Address C5h
Bit 7:0
Function
Conv.
EEPROM TReference 1
R/WP
Default value on delivery
Symbol TREF [15:8]
Bit 7
Value 00h to FFh
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
TREF [15:8] Preconfigured (Factory Calibrated)
Description Upper 8 bits of the TREF value.
Bit 1
Bit 0
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3.20.5. EEPROM PASSWORD REGISTERS
After a Power up and the first refreshment time tPREFR = ~66 ms, the EEPROM
Password registers 0 to 3 with the 32bit EEPROM Password are copied from the
EEPROM to the corresponding RAM mirror. The default values preset on delivery
are 00h.
C6h EEPROM Password 0 Bit 0 to 7 from 32-bit EEPROM Password. EEPW registers
(*WP) can be write-protected by password. RAM mirror is Write only. Returns 0
when read. EEPROM can be READ when unlocked.
Address C6h
Bit 7:0
Function
Conv.
EEPROM Password 0
*WP
Default value on delivery
Symbol
EEPW [7:0]
Bit 7
0 Value 00h to FFh
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
EEPW [7:0]
0
0
0
0
0
Description
Bit 0 to 7 from 32-bit EEPROM Password
Bit 1 0
Bit 0 0
C7h EEPROM Password 1 Bit 8 to 15 from 32-bit EEPROM Password.
EEPW registers (*WP) can be write-protected by password.
RAM mirror is Write only. Returns 0 when read. EEPROM can be READ when
unlocked.
Address C7h
Bit 7:0
Function
Conv.
EEPROM Password 1
*WP
Default value on delivery
Symbol EEPW [15:8]
Bit 7
0 Value 00h to FFh
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
EEPW [15:8]
0
0
0
0
0
Description Bit 8 to 15 from 32-bit EEPROM Password
Bit 1 0
Bit 0 0
C8h EEPROM Password 2 Bit 16 to 23 from 32-bit EEPROM Password.
EEPW registers (*WP) can be write-protected by password.
RAM mirror is Write only. Returns 0 when read. EEPROM can be READ when
unlocked.
Address C8h
Bit 7:0
Function
Conv.
EEPROM Password 2
*WP
Default value on delivery
Symbol EEPW [23:16]
Bit 7
0 Value 00h to FFh
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
EEPW [23:16]
0
0
0
0
0
Description Bit 16 to 23 from 32-bit EEPROM Password
Bit 1 0
Bit 0 0
C9h EEPROM Password 3 Bit 24 to 31 from 32-bit EEPROM Password.
EEPW registers (*WP) can be write-protected by password.
RAM mirror is Write only. Returns 0 when read. EEPROM can be READ when
unlocked.
Address C9h
Bit 7:0 November 2022
Function
Conv.
EEPROM Password 3
*WP
Default value on delivery
Symbol EEPW [31:24]
Bit 7
0 Value 00h to FFh
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
EEPW [31:24]
0
0
0
0
0
Description Bit 24 to 31 from 32-bit EEPROM Password
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Micro Crystal DTCXO Temp. Compensated Real-Time Clock Module
RV-3032-C7
3.20.6. EEPROM PASSWORD ENABLE REGISTER
After a Power up and the first refreshment time tPREFR = ~66 ms, the Password
Enable value EEPWE is copied from the EEPROM to the corresponding RAM mirror.
The default value preset on delivery is 00h.
CAh EEPROM Password Enable RAM mirror is Write only. Returns 0 when read.
Address CAh Bit
7:0
Function
Conv.
EEPROM Password Enable
WP
Default value on delivery
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4
Bit 3
EEPWE
0
0
Bit 2 0
Bit 1 0
Bit 0 0
Symbol EEPWE
Value 0 to 254
255
Description
EEPROM Password Enable
Password function disabled. When writing a value not equal 255, the password
function is disabled. 00h is the default value preset on delivery Password
function enabled. When writing a value of 255, the Password registers (39h to
3Ch) can be used to enter the 32-bit Password.
3.21. USER EEPROM
CBh to EAh User EEPROM 32 Bytes of User EEPROM for general purpose storage
are provided. Read: Always readable. Write: Can be write-protected by
password.
Address CBh to EAh
Function User EEPROM
Conv. R/WP
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
32 Bytes of non-volatile User EEPROM. Default values on delivery are 00h
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3.22. REGISTER RESET VALUES SUMMARY
Reset values; RAM, Address 00h to 25h:
Address
Function
Conv.
00h
100th Seconds
R
01h
Seconds
R/WP
02h
Minutes
R/WP
03h
Hours
R/WP
04h
Weekday
R/WP
05h
Date
R/WP
06h
Month
R/WP
07h
Year
R/WP
08h
Minutes Alarm
R/WP
09h
Hours Alarm
R/WP
0Ah
Date Alarm
R/WP
0Bh
Timer Value 0
R/WP
0Ch
Timer Value 1
R/WP
0Dh
Status
R/WP
0Eh
Temperature LSBs R/WP
0Fh
Temperature MSBs R
10h
Control 1
R/WP
11h
Control 2
R/WP
12h
Control 3
R/WP
13h
Time Stamp Contr. R/WP
14h
Clock Int. Mask
R/WP
15h
EVI Control
R/WP
16h
TLow Threshold
R/WP
17h
THigh Threshold R/WP
18h
TS TLow Count
R
19h
TS TLow Seconds
R
1Ah
TS TLow Minutes
R
1Bh
TS TLow Hours
R
1Ch
TS TLow Date
R
1Dh
TS TLow Month
R
1Eh
TS TLow Year
R
1Fh
TS THigh Count
R
20h
TS THigh Seconds
R
21h
TS THigh Minutes
R
22h
TS THigh Hours
R
23h
TS THigh Date
R
24h
TS THigh Month
R
25h
TS THigh Year
R
X = not defined, or defined under conditions.
Bit 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 0 0
Bit 6
Bit 5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0h Xh
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 4
Bit 3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00h XXh
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 2
0 0 0 0 0 0 0 0 0 0 0 0 0 X 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 0 0
Bit 1
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 0 0
Bit 0
0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 0 0
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Micro Crystal DTCXO Temp. Compensated Real-Time Clock Module
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Reset values; RAM, Address 26h to FFh:
Address
Function
Conv.
26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh to 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh
40h to 4Fh
50h to BFh CBh to FFh
TS EVI Count TS EVI 100th Secs. TS EVI Seconds TS EVI Minutes TS EVI Hours TS EVI Date TS EVI Month TS EVI Year RESERVED Password 0 Password 1 Password 2 Password 3 EE Address EE Data EE Command User RAM (16 Bytes) RESERVED RESERVED
R R R R R R R R Prot. W W W W R/WP R/WP WP
R/WP
Prot. Prot.
X = not defined, or defined under conditions.
Bit 7 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0
Bit 6 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0
Bit 5 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
Bit 4
Bit 3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00h
00h 00h
Bit 2 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
Bit 1 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
Bit 0 X 0 0 0 0 X X 0
0 0 0 0 0 0 0
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Default values on delivery; Configuration EEPROM with RAM mirror, Address C0h to CAh:
Address C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh
Function
EEPROM PMU
EEPROM Offset
EEPROM Clkout 1 EEPROM Clkout 2 EEPROM TReference 0 EEPROM TReference 1 EEPROM
Password 0 EEPROM Password 1 EEPROM Password 2 EEPROM Password 3 EEPROM PW
Enable
Conv. R/WP R/WP R/WP R/WP R/WP R/WP WP WP WP WP
WP
Bit 7 0 0 0 0
0 0 0 0 0
Bit 6 0 0 0 0
0 0 0 0 0
Bit 5 0 0
0
Bit 4 0 0
0
Bit 3 0 0
0
Bit 2 0 0
0
0
0
0
0
Preconfigured (Factory Calibrated)
Preconfigured (Factory Calibrated)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 1 0 0 0 0
0 0 0 0 0
Bit 0 0 0 0 0
0 0 0 0 0
Default values on delivery; User EEPROM, Address CBh to EAh:
Address CBh to EAh
Function
User EEPROM (32 Bytes)
Conv. R/WP
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
00h
Bit 2
Bit 1
Bit 0
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RV-3032-C7 reset values after power on (RAM) and default values on delivery (EEPROM) sorted by functions:
RAM, reset values:
Time (hh:mm:ss.00)
= 00:00:00.00 (100th Seconds = read only)
Date (YY-MM-DD)
= 00-01-01
Weekday
= 0
TS TLow Count
= 0
(read only)
TS TLow Time (hh:mm:ss) = 00:00:00
(read only)
TS TLow Date (YY-MM-DD) = 00-00-00
(read only)
TS THigh Count
= 0
(read only)
TS THigh Time (hh:mm:ss) = 00:00:00
(read only)
TS THigh Date (YY-MM-DD) = 00-00-00
(read only)
TS EVI Count
= X
(read only)
(if X = 1, LOW level was detected. Else X = 0)
TS EVI Time (hh:mm:ss.00) = 00:00:00.00 (read only)
TS EVI Date (YY-MM-DD) = 00-XX-XX (read only)
(if XX-XX = 01-01, LOW level was detected. Else XX-XX = 00-00)
Alarm function
= disabled, because AE_D = 0 = enabled and
Date Alarm value = 00h = not valid
Timer function
= disabled, Timer Clock Frequency = 4096 Hz
Update function
= disabled, second update is selected
Temperature value TEMP = 000h XXXh (read only)
Temperature Low function = disabled, TLow Threshold = 0°C
Temperature High function = disabled, THigh Threshold = 0°C
External Event function
= always enabled, falling edge is regarded as External Event on pin EVI
Time Stamp Temp. Low
= disabled, first event is selected
Time Stamp Temp. High
= disabled, first event is selected
Time Stamp Ext. Event
= always enabled, first event is selected
Backup Switchover Interrupt = disabled
(for enabling, see EEPROM)
Interrupts
= disabled (RAM enabled interrupts), see also Configuration EEPROM
EEPROM Memory Refresh = enabled
EEbusy status bit
= 1 0 (1 for the time tPREFR = ~66 ms, then it cleared to 0 automatically)
(read only)
STOP bit function
= disabled (prescaler not stopped)
ESYN bit function
= disabled (no time synchronization by External Event)
THF Flag
= 0
TLF Flag
= 0
UF Flag
= 0
TF Flag
= 0
AF Flag
= 0
EVF Flag
= X
(X = 1 when LOW level was detected on EVI pin, else X = 0)
PORF Flag
= 1
(can be cleared by writing 0 to the bit)
VLF Flag
= 0
EEF Flag
= 0
CLKF Flag
= 0
BSF Flag
= 0
Interrupt Controlled Clock = disabled, no interrupt source selected, CLKOUT delay disabled,
delay time tI2C:CLK = 1.4 ms selected, no interrupt delay
Password PW
= 00000000h (write only)
EE Address
= C0h
(points to EEPROM PMU)
EE Data
= 00h
EE Command
= 00h
(write only)
User RAM
= 00h
(16 Bytes)
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Configuration EEPROM with RAM mirror, default values on delivery:
Backup Switchover function = disabled
(for Interrupt, see RAM)
Power On Reset Interrupt = disabled
Voltage Low Interrupt
= disabled
Interrupts
= disabled (EEPROM enabled interrupts), see also RAM
Trickle Charger Mode
= disabled, TCR 0.6 k is selected
OFFSET value
= 0 (6 bits)
CLKOUT
= enabled, XTAL mode selected, F = 32.768 kHz
TREF value
= Preconfigured Value (16 bits) (may be changed by the user)
EEPROM Password EEPW = 00000000h (write only) (EEPROM readable when unlocked)
EEPROM Password Enable = disabled
(write only)
User EEPROM, default values on delivery: User EEPROM (32 Bytes) = 00h
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4. DETAILED FUNCTIONAL DESCRIPTION
4.1. POWER ON RESET (POR)
The power on reset (POR) is generated at start-up (see POWER ON RESET
INTERRUPT FUNCTION). All RAM registers including the Counter Registers are
initialized to their reset values and the Configuration EEPROM registers with
the RAM mirror registers are set to their preset default values. At power up a
refresh of the RAM mirror values by the values in the Configuration EEPROM is
automatically generated. The time of this first refreshment is tPREFR = ~66 ms
(see REGISTER RESET VALUES SUMMARY). The Power On Reset Flag PORF set to 1
indicates that a VDD startup from below the VPOR falling edge threshold (TYP
0.95 V) occurred in the VDD Power state, thereby generating a device POR. A
PORF value of 1 indicates that the time information is corrupted. The value 1
is retained until a 0 is written by the user. When PORIE bit (EEPROM C1h) is
set and the PORF flag was cleared beforehand, an interrupt signal on INT pin
can be generated when a Power On Reset occurs (see POWER ON RESET INTERRUPT
FUNCTION)
Hint: Resetting the PORF flag is actually not required to get a POR interrupt
on INT pin as the flag is automatically reset when VDD falls below VPOR (TYP
0.95 V) and is set again when VDD crosses the VPOR rising edge threshold (TYP
1.0 V) at startup. A POR interrupt is carried out in any case.
November 2022
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Rev. 1.2
Micro Crystal DTCXO Temp. Compensated Real-Time Clock Module
RV-3032-C7
4.2. AUTOMATIC BACKUP SWITCHOVER FUNCTION
Basic Hardware Definitions:
The RV-3032-C7 has two power supply pins.
o VDD
is the main power supply input pin.
o VBACKUP is the backup power supply input pin.
VTH:LSM (typical 2.0 V) is the backup switchover threshold voltage in Level Switching Mode.
A debounce logic provides a debounce time tDEB which will filter VDD oscillation when switchover function will switch back from VBACKUP to VDD. I2C access is again possible in VDD Power state (and if VDD 1.4 V) after
the debounce time tDEB. o tDEB MAX = 1 ms, when internal voltage was always above VLOW (typical 1.2 V). VLF = 0. o tDEB MAX = 1000 ms, when internal