intel AN 951 Stratix 10 I-O Limited FPGA Design Guidelines User Guide

intel AN 951 Stratix 10 I-O Limited FPGA Design Guidelines

Introduction

This document provides design guidelines specific to Intel® Stratix® 10 I/O Limited (IOL) FPGAs designated by ordering part numbers (OPN) ending with -NL. I/O Limited FPGAs limit transceiver utilization such that the one-way aggregate bandwidth is ≤499 Gbps and GPIO utilization to ≤700 I/O pins. Customers may find these devices useful where export restrictions constrain the usage of FPGAs with transceiver and I/O utilization above those limits. Unless otherwise specified, Intel Stratix 10 I/O Limited FPGAs behave identically to standard Intel Stratix 10 FPGAs. This document is based on Intel Quartus® Prime software version 21.1.

Overview

Intel Stratix 10 I/O Limited (IOL) FPGAs are designated with ordering part numbers (OPN) that end with an -NL suffix.
The Intel Quartus Prime software has restrictions on Intel Stratix 10 IOL FPGAs to limit GPIO, LVDS, and transceiver utilization.
The following table shows feature support for Intel Stratix 10 IOL FPGAs and Intel Stratix 10 standard OPN FPGAs.

Table 1. Intel Stratix 10 I/O Limited Device and Intel Stratix 10 Standard Device Feature Comparison:

performance difference.
Programming file compatibility| ( 1 )| ( 1 )
GPIO and LVDS| Maximum I/O pin count utilization ( 2 ) ( 3 )| >700 pins ( 4 )| ≤700 pins
Transceiver| Maximum bandwidth utilization ( 5 )| >499 Gbps| ≤499 Gbps
Dynamic reconfiguration| Yes| Yes ( 6 )
_ Note: _1. Refer to the _Device Configuration Guidelines_topic for details.

2.   GPIO and LVDS pin counts are limited to 700 pins by the Intel Quartus Prime software IOL restriction. LVDS pin count is 2 pins per pair.

3.   The I/O pin count includes general purpose I/O, LVDS I/O, and high voltage I/O.

4.   Maximum I/O pin count availability depends on device package selection.

5.   For details of the Intel Quartus Prime software bandwidth calculation, refer to the Transceiver Bandwidth _Calculation_topic.

6.   Enabling Dynamic Reconfiguration reduces transceiver maximum bandwidth per Intel Quartus Prime software IOL restrictions. Refer to the Dynamic Reconfiguration Status section in the Transceiver Bandwidth Calculation topic for more information.

Available Device Options and Ordering Part Numbers
This topic illustrates the mapping between available device options and their corresponding ordering codes, and shows the comparison between I/O Limited (IOL) and standard ordering codes.

Figure 1. Sample Ordering Code and Available Options for Intel Stratix 10 FPGAs with Optional NL Suffix

The following table shows the Intel Stratix 10 IOL FPGA ordering part numbers (OPN) and the equivalent Intel Stratix 10 standard device OPN. For information on ordering devices not listed in this table, contact your Intel representative.
Table 2. Intel Stratix 10 I/O Limited (IOL) FPGA OPN and the Equivalent Standard FPGA OPN

Intel Quartus Prime Software Guidelines

You must use the Intel Quartus Prime Pro Edition software version 21.1 or later to compile designs targeting Intel Stratix 10 I/O Limited (IOL) FPGAs.
The following topics provide guidance for migrating Intel Quartus Prime designs between Intel Stratix 10 standard OPN FPGAs and Intel Stratix 10 IOL FPGAs, and for Intel Quartus Prime software patch compatibility.

Design Migration
There are two methods for migrating a design between a standard Intel Stratix 10 FPGA and an Intel Stratix 10 I/O Limited (IOL) FPGA.
Design Migration Method 1: Change the Device OPN

1. In the Intel Quartus Prime software, click Assignments ➤ Device and select your targeted device.
2. You have the flexibility to change location and pin assignments, if desired. Click Yes when prompted, to have the Intel Quartus Prime software remove location and I/O assignments, or click No to keep your existing assignments.

Figure 2. Dialog Box to Remove Location and I/O Assignments

Design Migration Method 2: Use the Migration User Interface
The Migration User Interface helps in checking device compatibility and provides a comparison table—accessible from the Pin Migration View in the Pin Planner— showing migration results between the devices chosen for migration.

1. In the Intel Quartus Prime software, click Assignments ➤ Device.

2. Click the Migration Devices button at the bottom-right of the Device window.
   Figure 3. Example of the Device Dialog Box

3. In the Migration Devices dialog box, choose the compatible migration device that you want to target.
   Figure 4. Example of the Migration Devices Dialog Box

4. The Pin Migration View is available in the Pin Planner, and facilitates comparison between migration devices; it provides the following information:

   • Pin number
   • Migration devices
   • Pin finder
   • Migration result
   • Show only highlighted pins
   • Show migration differences
   • Export
   • Show column
     Open the Pin Migration View in the Pin Planner, by clicking View ➤ Pin Migration Window. You can access detailed information by right-clicking your selection in the Pin Migration View.

Figure 5. Example of the Pin Migration View

Intel Quartus Prime Software Patch Compatibility
The Intel Quartus Prime software patch for Intel Stratix 10 FPGAs with standard OPN is not compatible with Intel Stratix 10 I/O Limited (IOL) FPGAs, unless the patch specifies support.
To request an Intel Quartus Prime software patch for Intel Stratix 10 IOL FPGAs, contact My Intel Support.

Related Intel Quartus Prime Software Error Messages
When compiling designs targeting Intel Stratix 10 I/O Limited FPGAs, you might encounter compilation error messages as shown below.

Table 3. Related Intel Quartus Prime Software Error Messages

This design uses a device that is restricted to a maximum of 700 user-IOs. Currently, < I/O pin count > are being used!”| Error Message for > 700 Pins Utilization
The current device < device OPN >’s data-rate cannot exceed 499Gbps. The design’s TX data- rate is < TX cumulative data-rate >, and RX data-rate is < RX cumulative data-rate >.| Error Message for Design Exceeding Maximum Transceiver Bandwidth

Device Guidelines

Intel Stratix 10 I/O Limited (IOL) FPGAs support the same device configuration schemes as Intel Stratix 10 standard OPN FPGAs. The following topics provide guidelines for configuring GPIO, LVDS, and transceiver features to ensure successful design compilation on the Intel Stratix 10 IOL FPGA.

Device Configuration Guidelines
Intel Stratix 10 I/O Limited (IOL) FPGAs have unique device IDs that control device firmware to prevent loading of unauthorized programming files.
Programming File Compatibility
The following table shows programming file compatibility between standard OPN devices and equivalent IOL OPN devices. If you target the same design to both a standard OPN device and a compatible IOL OPN device, you can choose to compile the design using IOL OPN only.

Table 4. Programming File Compatibility Between Intel Stratix 10 FPGA with Standard OPN and Intel Stratix 10 I/O Limited FPGA with IOL OPN

| Intel Stratix 10 Standard Device| Intel Stratix 10 I/O Limited Device
---|---|---
Programming file generated with I/O Limited OPN| Yes| Yes
Programming file generated with standard OPN| Yes| No

Method to Identify a Device OPN from the .SOF Programming File
The following steps allow you to determine whether a given .SOF file targets an Intel Stratix 10 FPGA with Standard OPN or an Intel Stratix 10 FPGA with IOL OPN.

1. Go to the Intel Quartus Prime software command-line interface.
2. Change the working directory to locate the .SOF file: $cd
3. Type and run the quartus_pfg command: $ quartus_pfg -i .sof
4. In the displayed message, search for Device: .

The following figure illustrates an example of the displayed Intel Quartus Prime software message. The part number of the targeted Intel Stratix 10 I/O Limited FPGA ends with NL.

Figure 6. Example of Intel Quartus Prime Software Message showing IOL OPN in .SOF File

For information on Device ID, refer to Device ID in the Intel Stratix 10 JTAG Boundary-Scan Testing User Guide.
Related Information
Intel Stratix 10 JTAG Boundary-Scan Testing User Guide

GPIO and LVDS Guidelines
The following topics provide input/output (I/O) resource comparisons and design migration guidelines.

I/O Resource Comparison Between Standard OPN and IOL OPN Devices
The following table compares Intel Stratix 10 standard OPN and Intel Stratix 10 I/O Limited (IOL) OPN FPGAs.

Table 5. Similarities and Difference Between Intel Stratix 10 Standard OPN and I/O Limited OPN FPGAs

are described in the Intel Stratix 10 device pin-out files are identical. ( 2 )| None
I/O Utilization Limit| For F35 & F43 packages, the total I/O count utilization limits are identical between standard OPN and IOL OPN devices, because both have <700 I/O pins only.| For F50, F55 & F74 packages ( 3 ) the total I/O utilization is limited to a maximum of 700 pins for IOL OPNs. The 700 I/O pins can be any pin combination listed within the pin-out file. For designs that utilize more than 700 pins in standard OPN devices, the total I/O count must be reduced to

≤700 to fit in the IOL device.

Note: 1. Refer to Intel Stratix 10 General Purpose I/O User Guidefor information on Intel Stratix 10 I/O features.

2.   Refer to Intel ® Stratix ® 10 Device Pin-Out Files.

3.   Intel Stratix 10 IOL FPGAs with F50, F55 & F74 package options are not available currently. For information, contact your Intel representative.

Design Migration
When migrating a design from a larger I/O utilization count to a lesser I/O utilization count, you should evaluate the total device power and pin connections change.

Total Device Power Consumption
The device power consumption depends on the I/O utilization in the design. When I/O utilization changes after migrating a design from standard OPN to I/O Limited (IOL) OPN devices, you should evaluate power consumption using the Intel Quartus Prime Power Analyzer or Intel FPGA Power and Thermal Calculator, to achieve accurate power estimation.
For related information, refer to:

• Intel® FPGA Power and Thermal Calculator User Guide
• Intel® Quartus® Prime Pro Edition User Guide – Power Analysis and Optimization

Pin Connection for Unused Pins
If there are unused I/O pins after migrating a design from standard OPN to IOL OPN devices, you must connect the unused pins as defined in the Intel Quartus Prime software. The following steps illustrate this process:

1. In the Project Navigator in the Intel Quartus Prime software, right-click the OPN, and then click Device.
   Figure 7. Opening the Device Dialog Box

2. In the Device dialog box, click the Device and Pin Options button.
   Figure 8. Device and Pin Options Button in the Device Dialog Box

3. Navigate to the Unused Pins tab in the Category tree at the left side of the Device and Pin Options dialog box. Select your preferred setting from the dropdown list in the Reserve all unused pins section.
   Figure 9. Device and Pin Options Dialog Box

Error Message for > 700 Pins Utilization
When a design has I/O utilization exceeding 700 pins for a package that has more than 700 I/O pins, the Intel Quartus Prime software issues an error message during compilation.
Error message: This design uses a device that is restricted to a maximum of 700 user-IOs. Currently, <I/O pin count> are being used!”

Transceiver Guidelines
Intel Stratix 10 I/O Limited (IOL) FPGAs have additional Intel Quartus Prime Fitter placement restrictions that set the maximum transceiver bandwidth at 499 Gbps for respective TX accumulative data rate and RX accumulative data rate across all used transceiver channels in a design. Placement guidelines in the respective L/H/E/P-Tile Transceiver User Guide and in AN 778 apply for both standard Intel Stratix 10 and IOL Intel Stratix 10 FPGAs.
For related information, refer to:

• L- and H-Tile Transceiver PHY User Guide

• E-Tile Transceiver PHY User Guide
  Intel FPGA P-Tile Avalon Streaming IP for PCI Express Design Example User Guide

• P-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

• AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

Transceiver Bandwidth Calculation
The transceiver data rate for each channel that is applied to the design’s TX cumulative data rate and RX cumulative data rate is subject to two native PHY IP configurations: signal modulation mode, and dynamic reconfiguration status.

Signal Modulation Mode
By default, the native PHY IP applies non-return-to-zero (NRZ) modulation for
electrical signaling unless you select Pulse-Amplitude Modulation 4-Level (PAM4) in ETile.
L-Tile and H-Tile have NRZ modulation for electrical signaling only. When a channel uses NRZ, the data rate value counts as a single channel; however, when a link uses PAM4, the data rate value counts as two channels when it uses two physical channels.
Example of the calculation for a use model with one channel of 10 Gbps using NRZ and one link 56 Gbps using PAM4 signaling:
Bandwidth = (10Gbps x 1 channel) + (56 Gbps x 2 channels) = 122 Gbps

Dynamic Reconfiguration Status
For L-Tile, H-Tile, and E-Tile devices, the data rate used by the Intel Quartus Prime software for TX and RX data rate is subject to the status of the transceiver dynamic reconfiguration feature. When you have not enabled dynamic reconfiguration, the data rate is defined by the data rate attribute set in the native PHY IP. When you have enabled dynamic reconfiguration, the data rate is defined by the maximum data rate of the channel per the fastest transceiver specification of the L-Tile, H-Tile, or E-Tile.
Transceiver bandwidth is further reduced according to the following definitions:

• For L-Tile devices, the Intel Quartus Prime software applies the maximum data rate of the channel at transceiver speed grade 2, because L-Tile does not have transceiver speed grade 1.
• For H-Tile and E-Tile devices, the Intel Quartus Prime software applies the maximum data rate of the channel at transceiver speed grade 1, even though the I/O Limited (IOL) OPN transceiver speed grade is 2.

The following table illustrates an example that uses 10 Gbps across all channels, within an L-Tile, H-Tile, or E-Tile device.

Table 6. Effective Data Rate per Channel for Intel Quartus Prime Software Transceiver Bandwidth Calculation with Example of 10Gbps Native PHY IP

Dynamic Reconfiguration Status

Disable| Enable
Channel Location| Applied Data Rate per Channel (Gbps)| Channel Location| Applied Data Rate per Channel (Gbps)
L- Tile| H- Tile| E-Tile (NRZ/ PAM4)| L- Tile| H- Tile| E-Tile (NRZ/ PAM4)
23| 10| 10| 10 / 20| 23| 17.4| 17.4| 28.9 / 57.4
22| 10| 10| 10 / 20| 22| 26.6| 28.3| 28.9 / 57.4
21| 10| 10| 10 / 20| 21| 26.6| 28.3| 28.9 / 57.4
20| 10| 10| 10 / 20| 20| 17.4| 17.4| 28.9 / 57.4
19| 10| 10| 10 / 20| 19| 26.6| 28.3| 28.9 / 57.4
18| 10| 10| 10 / 20| 18| 26.6| 28.3| 28.9 / 57.4
17| 10| 10| 10 / 20| 17| 17.4| 17.4| 28.9 / 57.4
16| 10| 10| 10 / 20| 16| 26.6| 28.3| 28.9 / 57.4
15| 10| 10| 10 / 20| 15| 26.6| 28.3| 28.9 / 57.4
14| 10| 10| 10 / 20| 14| 17.4| 17.4| 28.9 / 57.4
13| 10| 10| 10 / 20| 13| 26.6| 28.3| 28.9 / 57.4
12| 10| 10| 10 / 20| 12| 26.6| 28.3| 28.9 / 57.4
11| 10| 10| 10 / 20| 11| 17.4| 17.4| 28.9 / 57.4
10| 10| 10| 10 / 20| 10| 26.6| 28.3| 28.9 / 57.4
9| 10| 10| 10 / 20| 9| 26.6| 28.3| 28.9 / 57.4
8| 10| 10| 10 / 20| 8| 17.4| 17.4| 28.9 / 57.4
continued…
Dynamic Reconfiguration Status

Disable| Enable
Channel Location| Applied Data Rate per Channel (Gbps)| Channel Location| Applied Data Rate per Channel (Gbps)
L- Tile| H- Tile| E-Tile (NRZ/ PAM4)| L- Tile| H- Tile| E-Tile (NRZ/ PAM4)
7| 10| 10| 10 / 20| 7| 26.6| 28.3| 28.9 / 57.4
6| 10| 10| 10 / 20| 6| 26.6| 28.3| 28.9 / 57.4
5| 10| 10| 10 / 20| 5| 17.4| 17.4| 28.9 / 57.4
4| 10| 10| 10 / 20| 4| 26.6| 28.3| 28.9 / 57.4
3| 10| 10| 10 / 20| 3| 26.6| 28.3| 28.9 / 57.4
2| 10| 10| 10 / 20| 2| 17.4| 17.4| 28.9 / 57.4
1| 10| 10| 10 / 20| 1| 26.6| 28.3| 28.9 / 57.4
0| 10| 10| 10 / 20| 0| 26.6| 28.3| 28.9 / 57.4

Error Message for Design Exceeding Maximum Transceiver Bandwidth
When a design exceeds the maximum transceiver bandwidth of ≤499Gbps, the Intel Quartus Prime Fitter issues error messages during compilation. The system displays information relating to the error, immediately before the error message. Information messages part 1 lists all the RX and TX channels and the data rate applied by the Fitter in transceiver bandwidth calculations, with one message line for each TX and RX channel. The message identifies whether the channel enables the transceiver dynamic reconfiguration feature. The following examples illustrate these information messages:

Information messages part 2 lists the TX cumulative data rate and RX cumulative data rate that is applied by the Intel Quartus Prime software to determine whether transceiver bandwidth limit is exceeded. The following examples illustrate these information messages:

An error message appears if the TX or RX cumulative data rate of the current design exceeds 499 Gbps.

The following figures show examples of Intel Quartus Prime software information messages and error messages for the following data rates, respectively:

• TX and RX cumulative data rate of 498.998400 Gbps
• TX and RX cumulative data rate of 499.200000 Gbps
• TX and RX cumulative data rate of 1184.00000 Gbps

Figure 10. Example of Intel Quartus Prime Software Information Messages with TX and RX Cumulative Data Rate of 498.998400 Gbps, with Transceiver Dynamic Reconfiguration Disabled

Figure 11. Example of Intel Quartus Prime Software Information and Error Messages with TX and RX Cumulative Data Rate of 499.200000 Gbps, with Transceiver Dynamic Reconfiguration Disabled

Figure 12. Example of Intel Quartus Prime Software Information and Error Messages With TX and RX Cumulative Data Rate of 1184.00000 Gbps, with Transceiver Dynamic Reconfiguration Enabled

Document Revision History for AN 951: Intel Stratix 10 I/O Limited FPGA

Design Guidelines

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