ANALOG DEVICES LT3077 Evaluation Board Photograph User Guide

ANALOG DEVICES LT3077 Evaluation Board Photograph

Specifications:

• Input voltage range: 0.6 V to 5.5 V
• BIAS voltage range: 2.375 V to 5.5 V
• Output voltage range: 0.5 V to 4.2 V
• Maximum output current: 3 A

Product Usage Instructions

Evaluating the LT3077:
The LT3077 is an Ultra-Low Noise, High PSRR, 85 mV Dropout Ultra-Fast Linear Regulator. To evaluate its performance, follow these steps:

1. Connect the EVAL-LT3077-AZ evaluation board.
2. Use DC power supplies within the specified voltage ranges.
3. Utilize multimeters for voltage and current measurements.
4. Connect electronic or resistive loads as needed.

Setting Output Voltage and Current Limit:
The output voltage and current limit can be set using jumpers and resistor combinations. Follow the selection matrix to program the desired output voltage. Choose between 3.72 A or 1.5 A output current limit, or disable the current limit altogether.

Turning the Regulator On/Off:
Use the jumper (JP1) to connect the EN pin to VBIAS to turn the output on, or ground to disable it.

Monitoring Output Status:
Monitor the output regulation status using the PG terminal, which indicates regulator output status and fault modes.

Connection Tips:
Use BNC connectors for noise and PSRR measurement, banana jacks to minimize voltage drops during connection, and ensure proper connections at VO+, VO-, and VI+ terminals for regulation and dropout monitoring.

FEATURES

• Input voltage range: 0.6 V to 5.5 V
• BIAS voltage range: 2.375 V to 5.5 V
• Jumpers program output voltage according to selection matrix: 0.5 V to 4.2 V
• Maximum output current: 3 A
• BNC connectors for noise and PSRR measurement
• Jumper and resistor combinations select either 3.72 A or 1.5 A output current limit or disable the programmed current limit
• Jumper turns the regulator on or off
• Terminal provides output regulation status monitoring
• Banana jacks minimize VIN and VOUT connection voltage drops
• VO+, VO-, and VI+ terminals for regulation and dropout monitor-ing
• 18-Lead (3mm × 3mm) LFCSP-RT Package

EVALUATION KIT CONTENTS

• EVAL-LT3077-AZ evaluation board

EQUIPMENT NEEDED

• DC power supplies
• Multimeters for voltage and current measurements
• Electronic or resistive load

DOCUMENTS NEEDED

• LT3077 datasheet

GENERAL DESCRIPTION

• The EVAL-LT3077-AZ evaluation board features the LT3077, a 3 A, ultra-low noise, high power-supply rejection ratio (PSRR), and 85 mV dropout ultra-fast linear regulator. The input voltage (VIN) range for the VIN power is from 0.6 V to 5.5 V. There are jumpers to set a 3-bit trilevel code that determines the output voltage (VOUT) at pre-programmed levels that range from 0.5 V to 4.2 V. The maximum output current is 3 A. The EVAL-LT3077-AZ requires an external BIAS voltage (VBIAS) that is at least 1.2 V higher than VOUT and is between 2.375 V and 5.5 V. The LT3077 of the EVAL-LT3077-AZ requires few external compo-nents, therefore, simplifying circuit design. External component choice, along with careful printed circuit board (PCB) design, helps optimize noise, PSRR, load transient response, and VOUT regulation performance. The LT3077 requires capacitors for the internal reference, power input, BIASF pin, and power output. The internal reference is bypassed with a 16 V, 0805 sized, 4.7 µF capacitor to reduce output noise and program the soft-start. Larger capacitor case sizes and higher voltage ratings decrease 1/f noise for otherwise comparable capacitors. The 22 µF capacitor at the circuit output was chosen for high-frequency PSRR performance and to minimize VOUT deviation during load transients.

• The capacitor that bypasses the VIN power for the LT3077 and the corresponding VIN PCB layout can affect PSRR (see the Best PSRR Performance: PCB Layout for Input Traces section for additional information). The EVAL-LT3077-AZ decouples the VIN power with a 47 µF capacitor. Less VIN capacitance can improve PSRR at high frequencies (Refer to the LT3077 data sheet for the minimum capacitor value required for VIN). Note that a bulk 220 µF tantalum polymer capacitor further reduces VIN variation during load transients and reduces input voltage ringing that can be caused by inductive input power leads. The PCB has a footprint for an optional
  Subminiature Version A (SMA) connector that allows a shielded VIN power connection to the PCB edge, if required.

• The EVAL-LT3077-AZ bypasses the BIASF pin with a 2.2 µF capacitor instead of the VBIAS supply input. Because the BIASF pin is isolated from VBIAS by a resistance that is internal to the LT3077, there is less PSRR degradation when BIASF is bypassed
  compared to when VBIAS is bypassed. Otherwise, the effect on PSRR of the VIN and VBIAS bypass capacitors is similar.

• The EVAL-LT3077-AZ has resistors that allow a CURRENT LIMIT jumper to select output current limits of either 1.5 A or 3.72 A. The CURRENT LIMIT jumper can also disable external current-limit programming by shorting the ILIM pin to ground. A POWER jumper (JP1) is available on the EVAL-LT3077-AZ to either connect the EN pin to VBIAS to turn the output on or to ground to disable the output. There is a PG terminal that is pulled up to VBIAS by a 51 kΩ resistor and pulled down by the open-drain, nega-tive channel metal-oxide-semiconductor (NMOS) PG pin output for indication of regulator output status and other fault modes.

• Banana jacks minimize voltage drops on VIN and VOUT connections. Bayonet Neill-Concelman (BNC) connectors provide low-noise connections to power VIN, VBIAS, and VOUT. The EVAL-LT3077-AZ PCB design uses a split capacitor technique to Kelvin connect the ground terminal of the REF capacitor to the ground terminal of the output capacitor, and the SENSE pin to the positive terminal of the output capacitor. The VO+, VO −, and VI+ terminals Kelvin connect to VIN and VOUT and are the optimum place to observe output voltage regulation and dropout voltage performance. There are test points for BIASF and REF voltages.

• The EVAL-LT3077-AZ has placeholders identified on the schematic as optional DNI components that make it convenient to add capaci-tance (see Figure 8).

• For full details on the LT3077, refer to the LT3077 datasheet, which must be consulted with this user guide when using the EVAL-LT3077-AZ evaluation board.

• The LT3077 of the EVAL-LT3077-AZ features an 18-Lead (3mm × 3mm) LFCSP-RT package. Proper board layout is essential for maximum thermal performance.

• Design files are available on the EVAL-LT3077-AZ evaluation board page.

PERFORMANCE SUMMARY

Specifications are at TA = 25°C, unless otherwise noted.

Table 1. Performance Summary

Parameter

INPUT VOLTAGE

Minimum Maximum

| Symbol

VIN

| ****

Test Conditions/Comments

IOUT = 300 mA

VOUT = 1.5 V, IOUT = 3 A

| ****

Min

5.5

21

| Typ| Max

0.6

| Unit

V V V

---|---|---|---|---|---|---
BIAS VOLTAGE

Minimum Maximum

| VBIAS| ****

VBIAS ≥ VOUT + 1.2 V

| ****

5.5

|  | ****

2.375

| ****

V V

OUTPUT VOLTAGE| VOUT| VOUT = 0.5 V, 50 mA ≤ IOUT ≤ 3 A, VIN = 0.8 V| 0.492| 0.500| 0.508| V
 |  | VOUT = 1.2 V, 10 mA ≤ IOUT ≤ 3 A, VIN = 1.5 V| 1.182| 1.200| 1.218| V
 |  | VOUT = 3.3 V, 10 mA ≤ IOUT ≤ 3 A, VIN = 3.6 V| 3.250| 3.300| 3.350| V
 |  | VOUT = 4.2 V, 10 mA ≤ IOUT ≤ 3 A, VIN = 4.5 V| 4.137| 4.200| 4.263| V
OUTPUT CURRENT| IOUT|  |  |  |  |
Maximum|  |  | 3|  |  | A
Minimum|  | VOUT < 0.8 V|  |  | 50| mA
 |  | VOUT ≥ 0.8 V|  |  | 10| mA
Limit2|  | ILIM resistor (RILIM) = 2 kΩ (1.5 A jumper position)| 1.41| 1.50| 1.59| A
 |  | RILIM = 806 Ω (3.72 A jumper position)| 3.61| 3.72| 3.83| A
BIAS PIN NAP MODE CURRENT| IBIAS_NAP| VBIAS = 5.5 V, EN = 0 V, R1 = open| 10| µA
IN PIN NAP MODE CURRENT| IIN_NAP| VIN = 5.5 V, EN = 0 V| 500| µA

1. The maximum power dissipation and, consequently, the maximum input voltage for an output that is programmed to 1 V with a 3 A load is set by the 60°C temperature rise of the LT3077 on the evaluation board. Higher input voltages can be reached if larger copper area or forced-air cooling is applied. In addition, consider the effect of ambient temperature and the maximum junction temperature that may occur. Refer to the LT3077 data sheet for more information.
2. The output current limit that occurs will be the lower of either the programmable current limit or the internal current limit. The internal current limit can be less than the programmable current limit for some conditions, such as high VBIAS and high temperature. Refer to the LT3077 data sheet for more information.

QUICK START PROCEDURE

To use the EVAL-LT3077-AZ to evaluate the performance of the LT3077, see Figure 2 for the proper measurement equipment setup and take the following steps:

1. With the input supplies and load off and turned down, make all the connections as shown in Figure 2. Ensure that the VO2, VO1, and VO0 jumpers to set VOUT are in the proper positions for the desired VOUT according to the VOUT selection matrix table in the LT3077 datasheet. In addition, ensure that the POWER jumper (JP1) is in the ON position, and that the CURRENT LIMIT jumper (JP5) is in the 3.72 A position.
2. Turn on the input and bias supplies and increase the input supply so it is at least 200 mV above the programmed output voltage. Adjust VBIAS so that it is between 2.375 V and 5.5 V and at least 1.2 V higher than the programmed VOUT for proper operation. Note that when setting the input and bias voltages, a VIN or VBIAS that is too close to the programmed VOUT (too low) can cause dropout operation and a loss of VOUT regulation. Also, a VIN that is too high above the output can increase power dissipation to an unacceptable level.
3. Increase the load to the desired IOUT. Readjust the input supply to be at least 200 mV above the programmed output voltage. Verify that VOUT is the expected voltage programmed by the jumpers. Note that if the VOUT is lower than expected, the load may be set too high. Temporarily disconnect the load to ensure that it is not set too high.
4. When the proper VOUT is established, adjust the input voltages and load within the operating ranges and observe the VOUT regulation, load transient response, and other parameters.
5. Refer to Application Note AN83 and Application Note AN159 for measuring output noise and PSRR. Note that J3, J4, and J5 are BNC connectors that are used for noise and PSRR measurements.
6. Note that the CURRENT LIMIT jumper can additionally select a 1.5 A current limit or the INTERNAL current limit that the LT3077 provides.
7. Monitor power good at the PG terminal.

PRINTED CIRCUIT BOARD LAYOUT

BEST PSRR PERFORMANCE: PCB LAYOUT FOR INPUT TRACES
For applications using the LT3077 for post-regulating switching converters, placing a capacitor directly at the LT3077 input results in AC current (at the switching frequency) flowing near the LT3077. Without careful attention to the PCB layout, this relatively high-frequency switching current generates an electromagnetic field (EMF) that couples to the LT3077 output, degrading its effective PSRR. While highly dependent on the PCB, the switching regulator, the input capacitor size, and among other factors, the PSRR can easily degrade at high frequencies. This degradation is present even if the LT3077 is desoldered from the board because it effectively degrades the PSRR of the PCB itself. While negligible for conventional low PSRR low dropout (LDO) regulators, the high PSRR of the LT3077 requires careful attention to higher- order parasitics to realize the full performance offered by the regulator. The EVAL-LT3077-AZ alleviates this degradation in PSRR by using a specialized layout technique. The VIN input trace and its corresponding return path (GND) are highlighted in red in Figure 4 and Figure 5. Figure 5 also shows the location of the C1 input capacitor and the connection between the GND return path for the VIN input trace and GND for the rest of the PCB. When an AC voltage is applied to the input of the EVAL-LT3077-AZ, AC current flows on the path formed through CIN1 by the input and the ground traces. Without the proper PCB layout, the AC current that flows on this path can generate EMFs that do not completely cancel and couple to the C3 output capacitor and related traces, making the PSRR appear worse than it actually is. With the input trace directly above the return path, the EMFs are in opposite directions, and consequently, cancel each other out. Ensure that these traces exactly overlap each other to maximize the cancellation effect and thus provide the maximum PSRR offered by the regulator.

PRINTED CIRCUIT BOARD LAYOUT

PCB LAYOUT FOR THE C3 OUTPUT CAPACITOR
As previously mentioned, the EVAL-LT3077-AZ PCB design uses a split-capacitor technique to Kelvin connect the ground terminal of the REF capacitor to the ground terminal of the C3 output capacitor and the SENSE pin to the positive terminal of the output capacitor (see Figure 6 and Figure 7). This Kelvin connection regulates the output voltage at the output capacitor, which in turn, optimizes noise, PSRR, load transient, and regulation performance that is all measured at the output capacitor. The split-capacitor technique is useful in this case because it makes it possible to relocate the regulation point, if desired. Regulation of the output voltage at a new location requires leaving the C3 output-capacitor location open and wiring the split-capacitor pads corresponding to the REF capacitor ground terminal and SENSE to the new output capacitor location. Additional capacitance located from SENSE to the REF ground between the regulation point and the LT3077 decreases sta-bility. The split-capacitor technique itself does not enhance LT3077 stability because of the type of pass transistor, even though the unity-gain bandwidth of the LT3077 bandwidth is relatively high and close to the self-resonance frequency of the output capacitor.

EVALUATION BOARD SCHEMATIC

ORDERING INFORMATION

Table 2. Bill of Materials

Item

Required Circuit Components

| Quantity1| Reference Designator| Part Description| Manufacturer, Part Number
---|---|---|---|---
1| 1| C1| 4.7 μF capacitor, X7R, 16 V, 10%, 0805, soft termination| Murata, GCJ21BR71C475KA01L
2| 1| C2| 2.2 μF capacitor, X7R, 10 V, 10%, 0603| Murata, GRM188R71A225KE15D
3| 1| C3| 22 μF capacitor, X7R, 16 V, 10%, 1210, AECQ200| Murata, GCM32ER71C226KE19L
4| 1| CIN1| 47 μF capacitor, X5R, 10 V, 10%, 1206| Murata, GRM31CR61A476KE15L
5| 1| U1| 3 A, ultra-low noise, high PSRR, 85 mV dropout, ultra-fast linear regulator| Analog Devices, Inc., LT3077ACRZ
Optional Evaluation Board|  |  |  |
Components|  |  |  |
1| 1| C4| 220 μF capacitor, tantalum polymer, 10 V,| AVX, TCJD227M010R0040
 |  |  | 20%,7343-31, 40 mΩ ESR|
2|  | C5, C7, C8, C9, C10| Capacitors, 1210, optional| Optional
3|  | C11, C12, CIN2| Capacitors, 1206, optional| Optional
4|  | C6| Capacitors, 0603, optional| Optional
5| 1| R1| 51 kΩ resistor, 5%, 1/10 W, 0603, AEC-Q200| Panasonic, ERJ-3GEYJ513V
6| 1| R2| 806 Ω resistor, 1%, 1/10 W, 0603, AEC-Q200| Panasonic, ERJ-3EKF8060V
7| 1| R3| 2 kΩ resistor, 1%, 1/10 W, 0603, AEC-Q200| Panasonic, ERJ-3EKF2001V
Hardware|  |  |  |
1| 5| E1, E2, E3, E4, E5| Test points, turret, 0.094″| Mill- Max,2501-2-00-80-00-00-07-0
2| 4| J1, J2, J6, J7| Connectors, banana jack, female, through-| Keystone, 575-4
 |  |  | hole,non-insulated, swage, 0.218″|
3| 3| J3, J4, J5| Connectors, RF, BNC, receptacle, jack, 5-| Amphenol RF, 112404
 |  |  | pin,straight, through-hole, 50 Ω|
4|  | J8| Connector, SMA jack, female, 50 Ω board| Optional
 |  |  | edge,end launch solder tab, optional|
5| 1| JP1| Connector, header, male, 1 x 3, 0.079″,| Würth Elektronik, 62000311121
 |  |  | through-hole|
6| 3| JP2, JP3, JP4| Connector, header, male, 1 x 4, 0.079″,| Würth Elektronik, 62000411121
 |  |  | through-hole|
7| 1| JP5| Connector, header, male, 2 x 3, 0.079″,| Würth Elektronik, 62000621121
 |  |  | through-hole|
8| 4| MP1 to MP4| Standoff, nylon, snap fit, 0.500″| Würth Elektronik, 702935000
9| 5| XJP1 to XJP5| Connector shunt, female, 2-position, 0.079″| Würth Elektronik, 60800213421

1 Blank cell is for optional components.

ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

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Furthermore, the license granted is expressly made subject to the following additional limitations:
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FAQ

Q: What equipment do I need for evaluating the LT3077?
A: You will need DC power supplies, multimeters, and electronic or resistive loads.

Q: How can I set the output voltage and current limit?
A: Use jumpers and resistor combinations according to the selection matrix provided in the user guide.

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