ANALOG DEVICES LTC3312SA 3.3V to 1.2V and1.8V at 6A 2MHz Dual Step-Down DC-DC Regulators Instructions

**ANALOG DEVICES LTC3312SA 3.3V to 1.2V and1.8V at 6A 2MHz Dual Step-Down DC- DC Regulators Instructions

**

DESCRIPTION

Demo Circuit 3091A features the LTC®3312SA, 5V, dual 6A/dual-phase 12A step- down DC/DC regulator IC. This demo circuit is configured as a 2MHz, 3.3V input buck regulator with dual 6A output at 1.2V and 1.8V.

The LTC3312SA features dual monolithic synchronous 6A step-down power stages in a 3mm × 4mm package for space saving applications with demanding performance requirements. Both bucks achieve high efficiency and fast transient response with small external components. The LTC3312SA can also be configured as a single output, dual-phase 12A step down converter. Please refer to DC3092A as a single output dual-phase application example. The LTC3312SA data sheet gives a complete description of its operation and application information.

The data sheet must be read in conjunction with this demo manual when evaluating or modifying this demo circuit. DC3091A supports three operation modes, including pulse skip, forced continuous and Burst Mode® operation.  The clock frequency and the operation mode are shared by  both regulators. User can select desired operation mode with JP1 jumper. Setting JP1 to FC/SYNC position also allows the LTC3312SA to sync to a clock frequency from 1MHz to 3MHz, operating in forced continuous mode. An EMI filter is included in this demo circuit for noise sensitive applications. To power with EMI filter, please apply input voltage via VIN EMI terminal.

Design files for this circuit board are available.
All registered trademarks and trademarks are the property of their respective owners.

PERFORMANCE SUMMARY

Specifications are at TA = 25°C

SYMBOL| PARAMETER| CONDITIONS| MIN| TYP| MAX| UNITS
---|---|---|---|---|---|---
VIN/VIN EMI| DC3091A Input Voltage Range| | 2.25| | 5.5| V
VOUT1| DC3091A Output 1 Voltage Range| | 1.174| 1.2| 1.226| V
VOUT2| DC3091A Output 2 Voltage Range| | 1.755| 1.8| 1.843| V
IOUT| DC3091A Output Current (Each Output)| | 6| A
fSW| Switching Frequency| | 1.8| | 2.2| MHz
EFF1| Output1 Efficiency| VIN = 3.3V, IOUT = 3A,VOUT1 = 1.2V| 92| %
EFF2| Output2 Efficiency| VIN = 3.3V, IOUT = 3A,VOUT2 = 1.8V| 94| %

BOARD PHOTO

Figure 1. DC3091A Demo Board

QUICK START PROCEDURE

Refer to Figure 2 for the proper measurement equipment setup and follow the procedure below:

NOTE: For accurate VIN, VOUT and efficiency measurements, measure VIN at the VIN SNSE and GND SNSN turrets, and measure VOUT at the VOUT SNSE and GND SNSE turrets. When measuring the input or output ripple, care must be taken to avoid a long ground lead on the oscilloscope probe. It is recommended to use technique shown in Figure 3a and Figure 3b for basic ripple measurement.

Prepare for the Test

• A. Select a power supply PS1 that can handle 5V of output voltage and 10A of output current, with internal current meter. If possible, connect PS1 Kelvin Sense terminals with VIN SNSE and GND SNSE turrets.

• B. Select two electronic loads LD1 and LD2 that can handle 2V of load voltage and up to 6A of load current in
  constant current mode.

• C. Select an oscilloscope with two or more channels and two voltage probes.

Test BUCK1 (VOUT1)

1. Connect PS1, LD1, VM1, VM2 and VM3 as shown in Figure 2. If the input EMI filter is desired, connect the input power supply to VIN EMI and GND.

2. Set the JP2 to HI position. Set LD1 to 0A. Slowly increase PS1 to 1V. If PS1 current reads less than 20mA, increase PS1 to 3.3V until VM1 reads 3.3V ±10mV. VM2 should read between 1.174V to 1.226V. VM3 should read above 3V.

3. Connect an oscilloscope voltage probe as shown in Figure 3a, between VOUT1 SNSE and GND1 SNSE turrets. Set channel to AC-coupled, voltage scale to 20mV, and time base to 10µs/div. Check VOUT1 ripple voltage. Output voltage ripple can also be measured with a low inductor connector on TP1, as shown in Figure 3b.

4. Increase the load by 1A intervals up to 6A and observe the voltage output regulation, ripple voltage, SW behavior and the voltage on the SSTT1 turret. Calculate Die temperature using the formula below:
   

5. If other operation modes are desired. Turn off PS1, set LD1 to 0A and set JP1 to FC/SYNC or BURST position. Turn on PS1, slowly increase LD1 and observe the change in PS1 output current, SW behavior and output ripple.

6. Optional: To change the frequency, remove R9. Install the desired RT resistor in the R4 location. Size the inductor, output capacitors and compensation components to provide the desired inductor ripple and a stable output. Refer to the LTC3312SA data sheet and LTPowerCAD for more information on choosing the required components.

7. Optional: To SYNC to a specific frequency, set JP1 to FC/SYNC position. Connect a waveform generator to MODE/SYNC turret. Please refer to LTC3312SA data sheet for synchronization signal requirements.

8. To test the transient response with a base load, add the desired resistor to produce a minimum load between VOUT and RSNS1 turrets (RL1 shown on Figure 2). Note that the total load resistance will be RL1 plus R11 (100mΩ). Adjust a signal generator with a 10ms period, 10% duty cycle and an amplitude from 1V to 2V to start.

9. Measure the RSNS1 voltage to observe the current, VRSNS1/100mΩ. Adjust the amplitude of the pulse to provide the desired transient. Connect signal generator SG1 between SG_INPUT and GND turrets. Adjust the rising and falling edge of the pulse to provide the desired ramp rate. Refer to the following equations for output current measurement:

10. When done, turn off SG1, PS1 and Load.
    Test BUCK2 (VOUT2)

11. Followsimilar steps forBUCK1 tests. Change the setup to LD2, VM4, VM5, SG2, RL2. VOUT2 should read between 1.755V to 1.843V when powered.

12. When done, turn off all the supplies and loads. Disconnect all the cables.

TEST SETUP

Figure 2. Test Setup for DC3091A Demo Board

_
Figure 3a. Technique for Measuring Output Ripple and Step Response
_

Figure 3b. Technique for Measuring Output Ripple and Step Response with a Low Inductance Connector (Not Supplied)

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. LTC3312SA Dual 6A Buck Typical Application Schematic

• Efficiency, VIN = 3.3V, VOUT = 1.2V All Modes
  
  Figure 5. Output1 Efficiency vs Load
  

• Efficiency, VIN = 3.3V, VOUT = 1.8V All Modes
  
  Figure 6. Output2 Efficiency vs Load
  

• Load Transient Response, Forced Continuous Mode
  
  figure 7. Output1 Load Step Response
  

• Load Transient Response, Forced Continuous Mode
  
  Figure 8. Output2 Load Step Respons
  

EMI TEST RESULTS

CISPR25 Conducted Emission Test with Class 5 Peak Limits (Voltage Method) (Supply)

DC3091A DEMO BOARD (WITH VOLTAGE APPLIED TO VIN EMI INPUT) 3.3V INPUT TO 1.2V AND 1.8V OUTPUT AT 4.8A, fSW = 2MHz
Figure 9. CISPR25 Conducted Emission Test with Class 5 Peak Limits (Voltage Method)

Radiated EMI Performance (CISPR25 Radiated Emissions Test with Class 5 Peak Limits)

DC3091A DEMO BOARD (WITH VOLTAGE APPLIED TO VIN EMI INPUT) 3.3V INPUT TO 1.2V AND 1.8V OUTPUT AT 4.8A, fSW = 2MHz
Figure 10. CISPR25 Radiated Emission Test with Class 5 Peak Limits

THEORY OF OPERATION

Introduction to the DC3091A

The DC3091A demonstration circuit features the LTC3312SA, 5V, Dual 6A/Dual- Phase 12A step-down DC/ DC regulator. The LTC3312SA contains two monolithic, constant frequency, current mode step-down DC/DC converters. An oscillator, shared by two converters, with frequency set by a resistor on the RT pin, turns on the internal top power switch at the beginning of each clock cycle. The beginning of each clock cycle of the two converters are 180-degree out of phase. Current in the inductor then increases until the top switch comparator trips and turns off the top power switch. The peak inductor current, at which the top switch turns off, is controlled by the voltage on the internal ITH node, which is the output of the error amplifier. The internal ITH node is connected with internal compensator to stabilize the control loop. The error amplifier servos the ITH node by comparing the voltage on the VFB pin with an internal 500mV reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference leading the error amplifier to raise the ITH voltage until the average inductor current matches the new load current. When the top switch turns off, the synchronous bottom power switch turns on until the next clock cycle begins. In pulse skip mode and Burst Mode, the bottom switch also turns off when inductor current falls to zero. If overload conditions result in excessive current flowing through the bottom switch, the next clock cycle will be delayed until the switch current returns to a safe level. In Burst Mode, the error amplifier and most part of the internal circuitry can be turned off until output voltage trips an output low comparator, during extreme light load condition, to improve light load efficiency.

If the ENx pin is low, the corresponding converter in LTC3312SA is in shutdown and in a low quiescent current state. When the ENx pin is above its threshold, the corresponding switching converter will be enabled.

The MODE/SYNC pin synchronizes the switching frequency to an external clock. It also sets the PWM mode.

The PWM modes of operation are Burst, Pulse Skip and Forced Continuous. See the LTC3312SA data sheet for more detailed information.

The maximum allowable operating frequency is influenced by the minimum on time of the top switch, the ratio of VOUT to VIN and the available inductor values. The maximum allowable operating frequency may be calculated in the formula below.

Select an operating switching frequency below fSW(MAX). Typically, it is desired to obtain an inductor current of 30% of the maximum LTC3312 operating load, 6A. Use the formulas below to calculate the inductor value to obtain a 30% (1.8A) inductor ripple for the operating frequency.

The overall control loop of the converter can be tuned by output capacitors and feed forward capacitors. The LTC3312SA has been designed to operate at a high bandwidth for fast transient response capabilities. This reduces required output capacitance to meet the desired transient voltage range. C6 along with R11, or C28 along with R14, provides a phase lead which will improve the phase margin.

Loop stability is generally measured using the Bode Plot method of plotting loop gain in dB and phase shift in degrees. The 0dB crossover frequency should be less the 1/6 of the operating frequency to reduce the effects of added phase shift of the modulator. The control loop phase margin goal should be 45° or greater and a gain margin goal of 8dB or greater.

PARTS LIST

ITEM| QTY| REFERENCE| PART DESCRIPTION| MANUFACTURER/PART NUMBER
---|---|---|---|---
Required Circuit Components
1| 5| C1, C13-C16| CAP., 1µF, X7T, 6.3V, 20%, 0201| MURATA, GRM033D70J105ME01D
2| 2| C2, C3| CAP., 22µF, X5R, 10V, 20%, 0603| MURATA, GRM188R61A226ME15D
3| 4| C4, C5, C17, C18| CAP., 47µF, X6S, 6.3V, 20%, 0805| TAIYO YUDEN, JMK212BC6476MG-T
4| 1| C6| CAP., 10pF, C0G/NP0, 50V, ±0.5pF, 0402| TDK, C1005C0G1H100D050BA
5| 1| C19| CAP., 22pF, C0G, 50V, 10%, 0402| AVX, 04025A220KAT2A
6| 2| C29, C35| CAP., 0.015µF, X7R, 16V, 10%, 0402| MURATA, GRM155R71C153KA01J
7| 1| L1| IND., 220nH, 20%, 6.7A, 13mΩ| TDK, TFM252012ALMAR22MTAA
8| 1| L2| IND., 330nH, 20%, 19mΩ| MURATA, DFE252012F-R33M=P2
9| 1| R1| RES., 140k, 1%, 1/16W, 0402| NIC, NRC04F1403TRF
10| 1| R2| RES., 100k, 1%, 1/16W, 0402| NIC, NRC04F1003TRF
11| 1| R14| RES., 107k, 1%, 1/16W, 0402| NIC, NRC04F1073TRF
12| 1| R15| RES., 41.2k, 1%, 1/16W, 0402| VISHAY, CRCW040241K2FKED
13| 1| U1| IC, 5V, DUAL 6A/DUAL PHASE 12A STEP-DOWN DC/DC REGULATOR, LQFN| ANALOG DEVICES, LTC3312SAAV#PBF
Additional Demo Board Circuit Components
1| 2| C7, C8| CAP., 470µF, TANT, POSCAP, 6.3V, 20%, 7343, 18mΩ| PANASONIC, 6TPE470MI
2| 1| C9| CAP., 0.1µF, X7R, 25V, 10%, 0402| MURATA, GCM155R71E104KE02D
3| 2| C10, C11| CAP., 10µF, X7S, 6.3V, 20%, 0603| TDK, C1608X7S0J106M080AC
4| 2| C12, C24| CAP., 0.22µF, X7R, 6.3V, 20%, 0603| JOHANSON DIELECTRICS, 6R3X14W224MV4T
5| 2| C22, C23| CAP., 1000pF, X7R, 50V, 20%, 0402, 3-TERM, X2Y EMI FILTER| JOHANSON DIELECTRICS, 500X07W102MV4T
6| 1| L3| IND., 100Ω AT 100MHz, FERRITE BEAD, 25%, 8A, 6mΩ, 1812| WURTH ELEKTRONIK, 74279226101
7| 2| Q1, Q2| XSTR., MOSFET, N-CH, 40V, 15.9A, PPAK SO-8| VISHAY, SIR426DP-T1-GE3
8| 2| R3, R12| RES., 20Ω, 1%, 1/16W, 0402| NIC, NRC04F20R0TRF
9| 3| R5, R10, R18| RES., 10k, 5%, 1/10W, 0402| PANASONIC, ERJ2GEJ103X
10| 2| R6, R16| RES., 1M, 1%, 1/16W, 0402| NIC, NRC04F1004TRF
11| 2| R7, R17| RES., 249k, 1%, 1/16W, 0402| NIC, NRC04F2493TRF
12| 2| R8, R13| RES., 100k, 5%, 1/16W, 0402| YAGEO, RC0402JR-07100KL
13| 1| R9| RES., 0Ω, 1/16W, 0402| NIC, NRC04ZOTRF
14| 2| R11, R19| RES., 0.1Ω, 1%, 2W, 2512, SENSE| IRC, LRC-LR2512LF-01-R100-F
15| 2| TP1, TP2| CONN., U.FL, RECEPT, ST SMD, 0Hz TO 6GHz 50Ω| HIROSE ELECTRIC, U.FL-R-SMT-1(10)
16| 2| TP1_PLUG, TP2_PLUG| CONN U.FL PLUG STR 50Ω SMD| HIROSE ELECTRIC, U.FL- PR-SMT2.5-1(10)
Hardware: For Demo Board Only
1| 18| E1-E3, E5, E12, E14-E16, E19, E21, E26-E29, E30, E32-E34| TEST POINT, TURRET, 0.064″ MTG. HOLE, PCB 0.062″ THK| MILL-MAX, 2308-2-00-80-00-00-07-0
2| 9| E4, E7, E11, E13, E18, E20, E24, E25, E31| TEST POINT, TURRET, 0.094″ MTG. HOLE, PCB 0.062″ THK| MILL-MAX, 2501-2-00-80-00-00-07-0
3| 7| E6, E8-E10, E17, E22, E23| CONN., BANANA JACK, FEMALE, THT, NON- INSULATED, SWAGE, 0.218″| KEYSTONE, 575-4
4| 1| JP1| CONN., HDR, MALE, 1×4, 2mm, VERT, ST, THT| WURTH ELEKTRONIK, 62000411121
5| 2| JP2, JP3| CONN., HDR, MALE, 1×3, 2mm, VERT, ST, THT| WURTH ELEKTRONIK, 62000311121
5| 4| MP1-MP4| STANDOFF, NYLON, SNAP-ON, 0.50″| WURTH ELEKTRONIK, 702935000
6| 3| XJP1, XJP2, XJP3| CONN., SHUNT, FEMALE, 2 POS, 2mm| WURTH ELEKTRONIK, 60800213421

SCHEMATIC DIAGRAM

• PCA ADDITIONAL PARTS
• MP1: STANDOFF,NYLON,SNAP-ON,0.50″
• MP2: STANDOFF,NYLON,SNAP-ON,0.50″
• MP3: STANDOFF,NYLON,SNAP-ON,0.50″
• MP4: STANDOFF,NYLON,SNAP-ON,0.50″
• LB1: LABEL
• PCB1: PCB, DC3091A REV03

NOTES: UNLESS OTHERWISE SPECIFIED

1. RESISTORS: OHMS, 0402, 1%, 1/16W
2. CAPACITORS: 0402

CUSTOMER NOTICE

ANALOG DEVICES HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER’S RESPONSIBILITY TO
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT ANALOG DEVICES
APPLICATIONS ENGINEERING FOR ASSISTANCE.

THIS CIRCUIT IS PROPRIETARY TO ANALOG DEVICES AND SUPPLIED FOR USE WITH ANALOG DEVICES PARTS

APPROVALS

PCB DES. NC
APP ENG.: WL

TITLE: SCHEMATIC
3.3V VIN, DUAL 6A, 2MHz SYNCHRONOUS STEP-DOWN REGULATORS WITH 1.2V AND 1.8V OUTPUTS

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

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