Compulab UCM-iMX93 Module with WiFi 5 and Bluetooth 5.3 User Guide
- June 14, 2024
- Compulab
Table of Contents
- UCM-iMX93 Module with WiFi 5 and Bluetooth 5.3
- Specifications
- Introduction
- About This Document
- UCM-iMX93 Part Number Legend
- Related Documents
- Section 4.17: JTAG
- Section 4.18: GPIO
- Section 6: CARRIER BOARD INTERFACE
- Section 8: APPLICATION NOTES
- Q: Where can I find the latest revision of the UCM-iMX93
- Q: How can I decode the UCM-iMX93 part number?
- Q: Where can I find additional developer resources for the
UCM-iMX93 Module with WiFi 5 and Bluetooth 5.3
Specifications
- Product Name: UCM-iMX93
- Manufacturer: Compulab Ltd.
- Part Number: UCM-iMX93
- Address: P.O. Box 687 Yokneam Illit 20692 ISRAEL
- Telephone: +972 (4) 8290100
- Website: https://www.compulab.com
- Fax: +972 (4) 8325251
- Revision Date: October 2023
Introduction
About This Document
This document is part of a set of reference documents providing
information necessary to operate and program CompuLab UCM-iMX93
System-on-Module.
UCM-iMX93 Part Number Legend
Please refer to the CompuLab website ‘Ordering information’
section to decode the UCM-iMX93 part number:
https://www.compulab.com/products/computer-on-modules/ucm-imx93-nxp-i-mx9-som-
system-on-module-computer/#ordering.
Related Documents
For additional information, refer to the documents listed
below:
Product Usage Instructions
Section 4.17: JTAG
The JTAG interface allows for debugging and programming of the
UCM-iMX93 module. Follow the instructions provided in the UCM-iMX93
Reference Guide to properly connect and utilize the JTAG
interface.
Section 4.18: GPIO
The GPIO (General Purpose Input/Output) pins on the UCM-iMX93
module can be used for various purposes such as controlling
external devices or receiving signals. Please refer to the
UCM-iMX93 Reference Guide for detailed information on GPIO pinout
and usage.
Section 6: CARRIER BOARD INTERFACE
6.1 Connectors Pinout
The UCM-iMX93 module has various connectors for interfacing with
a carrier board. The pinout information for these connectors can be
found in section 6.1 of the UCM-iMX93 Reference Guide.
6.2 Mating Connectors
To properly connect the UCM-iMX93 module to a carrier board,
compatible mating connectors should be used. Refer to section 6.2
of the UCM-iMX93 Reference Guide for recommended mating connectors
and their specifications.
6.3 Mechanical Drawings
Detailed mechanical drawings and dimensions of the UCM-iMX93
module can be found in section 6.3 of the UCM-iMX93 Reference
Guide. These drawings can be useful for designing custom enclosures
or mounting brackets.
Section 8: APPLICATION NOTES
8.1 Carrier Board Design Guidelines
If you are designing a carrier board for the UCM-iMX93 module,
section 8.1 of the UCM-iMX93 Reference Guide provides guidelines
and recommendations for designing a compatible and efficient
carrier board.
8.2 Carrier Board Troubleshooting
In case of any issues or troubleshooting requirements related to
the UCM-iMX93 module and its carrier board, section 8.2 of the
UCM-iMX93 Reference Guide offers troubleshooting tips and solutions
for common problems.
FAQ
Q: Where can I find the latest revision of the UCM-iMX93
Reference Guide?
A: Please visit the CompuLab website at https://www.compulab.com to find the
latest revision of the UCM-iMX93 Reference Guide.
Q: How can I decode the UCM-iMX93 part number?
A: To decode the UCM-iMX93 part number, please refer to the
‘Ordering information’ section on the CompuLab website at
https://www.compulab.com/products/computer-on-modules/ucm-imx93-nxp-i-mx9-som-
system-on-module-computer/#ordering.
Q: Where can I find additional developer resources for the
UCM-iMX93 module?
A: Additional developer resources for the UCM-iMX93 module can
be found on the CompuLab website at
https://www.compulab.com/products/computer-on-modules/ucm-imx93-nxp-i-mx9-som-
system-on-module-computer/#devres.
UCM-iMX93
Reference Guide
Legal
© 2023 Compulab Ltd. All Rights Reserved. No part of this document may be
photocopied, reproduced, stored in a retrieval system, or transmitted, in any
form or by any means whether, electronic, mechanical, or otherwise without the
prior written permission of Compulab Ltd. No warranty of accuracy is given
concerning the contents of the information contained in this publication. To
the extent permitted by law, no liability (including liability to any person
by reason of negligence) will be accepted by Compulab Ltd., its subsidiaries
or employees for any direct or indirect loss or damage caused by omissions
from or inaccuracies in this document. Compulab Ltd. reserves the right to
change details in this publication without notice. Product and company names
herein may be the trademarks of their respective owners.
Compulab Ltd. P.O. Box 687 Yokneam Illit 20692 ISRAEL Tel: +972 (4) 8290100
https://www.compulab.com Fax: +972 (4) 8325251
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UCM-iMX93 Reference Guide
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Table of Contents
Table of Contents
1 INTRODUCTION …………………………………………………………………………………………….. 6 1.1 About This Document
…………………………………………………………………………………. 6 1.2 UCM-iMX93 Part Number
Legend…………………………………………………………………. 6 1.3 Related Documents
……………………………………………………………………………………. 6
2 OVERVIEW ……………………………………………………………………………………………………. 7 2.1 Highlights
…………………………………………………………………………………………………. 7 2.2 Block Diagram
…………………………………………………………………………………………… 7 2.3 Specifications
……………………………………………………………………………………………. 8
3 CORE SYSTEM COMPONENTS ………………………………………………………………………… 10 3.1 i.MX93 System-on-
Chip …………………………………………………………………………….. 10 3.2 Memory
…………………………………………………………………………………………………. 10 3.2.1 DRAM
…………………………………………………………………………………………….. 10 3.2.2 Bootloader and General Purpose
Storage …………………………………………….. 10
4 PERIPHERAL INTERFACES………………………………………………………………………………. 11 4.1 Display
Interfaces …………………………………………………………………………………….. 12 4.1.1 MIPI-
DSI………………………………………………………………………………………….. 12 4.1.2 LVDS Interface
…………………………………………………………………………………. 12 4.2 Camera
Interface……………………………………………………………………………………… 13 4.3 Audio Interfaces
………………………………………………………………………………………. 13 4.3.1
S/PDIF…………………………………………………………………………………………….. 13 4.3.2 SAI
…………………………………………………………………………………………………. 14 4.3.3 MQS
………………………………………………………………………………………………. 15 4.4 Ethernet
…………………………………………………………………………………………………. 16 4.4.1 Gigabit Ethernet
………………………………………………………………………………. 16 4.4.2 RGMII
…………………………………………………………………………………………….. 17 4.5 WiFi and Bluetooth Interfaces
……………………………………………………………………. 19 4.6 USB…………………………………………………………………………………………………………
19 4.7 MMC / SD /SDIO ………………………………………………………………………………………. 20 4.8 FlexSPI
……………………………………………………………………………………………………. 21 4.9 UART
……………………………………………………………………………………………………… 22 4.10 CAN-FD
………………………………………………………………………………………………. 25 4.11
SPI……………………………………………………………………………………………………… 26 4.12 I2C
…………………………………………………………………………………………………….. 28 4.13 I3C
…………………………………………………………………………………………………….. 29 4.14 Timer/Pulse Width
Modulation………………………………………………………………. 30 4.15
ADC……………………………………………………………………………………………………. 31 4.16 Tamper
………………………………………………………………………………………………. 31
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Table of Contents
4.17 JTAG…………………………………………………………………………………………………… 31 4.18 GPIO
………………………………………………………………………………………………….. 31
5 SYSTEM LOGIC …………………………………………………………………………………………….. 34 5.1 Power
Supply…………………………………………………………………………………………… 34 5.2 I/O Voltage Domains
………………………………………………………………………………… 34 5.3 System and Miscellaneous Signals
………………………………………………………………. 34 5.3.1 Power management
…………………………………………………………………………. 34 5.4 Reset
……………………………………………………………………………………………………… 35 5.5 Boot Sequence
………………………………………………………………………………………… 35 5.6 Signal Multiplexing Characteristics
……………………………………………………………… 36 5.7 RTC …………………………………………………………………………………………………………
40 5.8 Reserved Pins ………………………………………………………………………………………….. 40 5.9 Not Connected
Pins ………………………………………………………………………………….. 40
6 CARRIER BOARD INTERFACE………………………………………………………………………….. 41 6.1 Connectors
Pinout ……………………………………………………………………………………. 41 6.2 Mating Connectors
…………………………………………………………………………………… 46 6.3 Mechanical
Drawings………………………………………………………………………………… 46
7 OPERATIONAL CHARACTERISTICS…………………………………………………………………… 48 7.1 Absolute
Maximum Ratings ……………………………………………………………………….. 48 7.2 Recommended Operating
Conditions ………………………………………………………….. 48 7.3 Typical Power Consumption
………………………………………………………………………. 48 7.4 ESD
Performance……………………………………………………………………………………… 48
8 APPLICATION NOTES ……………………………………………………………………………………. 49 8.1 Carrier Board
Design Guidelines …………………………………………………………………. 49 8.2 Carrier Board
Troubleshooting …………………………………………………………………… 49
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Revision Notes
Table 1 Revision Notes
Date Mar 2023 Aug 2023 Sep 2023
Oct 2023
Description
· Initial release · Added description of pin P1-17 in table 51 · Added power
consumption data in section 7.3 · Updated V_SOM maximal allowed voltage ·
Updated specifications table removed C1500D option
Please check for a newer revision of this manual at the CompuLab website https://www.compulab.com. Compare the revision notes of the updated manual from the website with those of the printed or electronic version you have.
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UCM-iMX93 Reference Guide
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Introduction
1
INTRODUCTION
1.1
About This Document
This document is part of a set of reference documents providing information necessary to operate and program CompuLab UCM-iMX93 System-on-Module.
1.2
UCM-iMX93 Part Number Legend
Please refer to the CompuLab website `Ordering information’ section to decode
the UCM-iMX93 part number: https://www.compulab.com/products/computer-on-
modules/ucm-imx93-nxp-i-
mx9-som-system-on-module-computer/#ordering.
1.3
Related Documents
For additional information, refer to the documents listed in Table 2.
Table 2
Related Documents
Document
UCM-iMX93 Developer Resources
i.MX93 Reference Manual
i.MX93 Datasheet
Location
https://www.compulab.com/products/computer-onmodules/ucm-imx93-nxp-i-mx9-som-
system-on-modulecomputer/#devres https://www.nxp.com/products/processors-
andmicrocontrollers/arm-processors/i-mx-
applicationsprocessors/i-mx-9-processors/i-mx-93-applicationsprocessor-family-
arm-cortex-a55-ml-acceleration-powerefficient-mpu:i.MX93
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2
OVERVIEW
2.1
Highlights
· NXP i.MX93 processor, up-to 1.7GHz · Up to 2GB LPDDR4 and 64GB eMMC · Integrated AI/ML Neural Processing Unit · LVDS, MIPI-DSI and MIPI-CSI · Certified 802.11ac WiFi, BT 5.3 · GbE, RGMII, 2x USB, 2x CAN-FD, 7x UART · Tiny size and weight – 28 x 38 x 4 mm, 7 gram
2.2
Block Diagram
Figure 1 UCM-iMX93 Block Diagram
Overview
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2.3
Overview
Specifications
The “Option” column specifies the CoM/SoM configuration option required to have the particular feature. When a CoM/SoM configuration option is prefixed by “NOT”, the particular feature is only available when the option is not used. “+” means that the feature is always available.
Table 3 Features and Configuration options
Feature
Description
CPU
NPU Real-Time Co-processor
RAM Storage
CPU Core and Graphics NXP i.MX9352, dual-core ARM Cortex-A55, 1.7GHz NXP
i.MX9331, single-core ARM Cortex-A55, 1.7GHz AI/ML Neural Processing Unit Arm®
EthosTM U-65 microNPU ARM Cortex-M33, 250Mhz
Memory and Storage 512MB 2GB, LPDDR4 eMMC flash, 8GB – 64GB
Display, Camera and Audio
Display Touchscreen Camera Audio
MIPI-DSI, 4 data lanes, up to 1080p60 LVDS, 4 lanes, up to 1366×768 p60 Capacitive touch-screen support through SPI and I2C interfaces MIPI-CSI, 2 data lanes Up-to 2x I2S / SAI S/PDIF input/output
Ethernet RGMII
WiFi Bluetooth
Network
Gigabit Ethernet port (MAC+PHY) Primary RGMII Secondary RGMII Certified
802.11ac WiFi NXP 88W8997 chipset Bluetooth 5.3 BLE
USB UART CAN bus
SD/SDIO
SPI I2C ADC PWM GPIO
RTC JTAG
I/O
2x USB2.0 dual-role ports Up to 7x UART Up-to 2x CAN-FD 1x SD/SDIO Additional
1x SD/SDIO Up to 7x SPI Up to 6x I2C 4x general-purpose ADC channels Up to 6x
PWM signals Up to 79x GPIO (multifunctional signals shared with other
functions)
System Logic
Real-time clock, powered by external battery JTAG debug interface
Option
C1700D C1700S C1700D
- D N
+ + + + + +
+ not E -
WB
+ + + + not WB + +
+ +
+ +
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Table 4 Electrical, Mechanical and Environmental Specifications
Electrical Specifications
Supply Voltage Digital I/O voltage Power consumption
3.45V to 5.5V 3.3V / 1.8V 0.5 – 3 W, depending on system load and board configuration
Mechanical Specifications
Dimensions Weight Connectors
28 x 38 x 4 mm 7 gram 2 x 100 pin, 0.4mm pitch
Environmental and Reliability
MTTF
Operation temperature (case)
Storage temperature
Relative humidity
Shock Vibration
200,000 hours Commercial: 0° to 70° C Extended: -20° to 70° C Industrial: -40° to 85° C
-40° to 85° C
10% to 90% (operation) 05% to 95% (storage) 50G / 20 ms 20G / 0 – 600 Hz
Overview
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Core System Components
3
CORE SYSTEM COMPONENTS
3.1
i.MX93 System-on-Chip
The i.MX 93 System-on-Chip (SoC) includes powerful dual Arm® Cortex®-A55 processors with speeds up to 1.7 GHz integrated with a NPU that accelerates machine learning inference. A general-purpose Arm® Cortex®-M33 running up to 250 MHz is for real-time and low-power processing.
Figure 2 i.MX 93 Block Diagram
3.2
3.2.1
3.2.2
Memory
DRAM
UCM-iMX93 is equipped with up to 2GB of onboard LPDDR4 memory. The LPDDR4
channel is 16bits wide.
Bootloader and General Purpose Storage
UCM-iMX93 uses on-board non-volatile memory (eMMC) storage for storing the
bootloader. The remaining eMMC space is intended to store the operating system
(kernel & root filesystem) and general purpose (user) data.
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Peripheral Interfaces
4
PERIPHERAL INTERFACES
UCM-iMX93 implements a variety of peripheral interfaces through two 100-pin
(0.4mm pitch) carrier board connectors. The following notes apply to
interfaces available through the carrierboard connectors:
· Some interfaces/signals are available only with/without certain
configuration options of
the UCM-iMX93 SoM. The availability restrictions of each signal are described
in the “Signals description” table for each interface.
· Some of the UCM-iMX93 carrier board interface pins are multifunctional. Up
to 8
functions (ALT modes) are accessible through each multifunctional pin. For
additional details, please refer to chapter 5.6.
· UCM-iMX93 uses different I/O voltage domains to power different groups of
digital
signals. Some pin operate at 3.3V, some at 1.8V. Voltage domain of each signal
is specified in the “Signals description” table for each interface.
The signals for each interface are described in the “Signal description” table
for the interface in question. The following notes provide information on the
“Signal description” tables:
· “Signal name” The name of each signal with regards to the discussed
interface. The
signal name corresponds to the relevant function in cases where the carrier
board pin in question is multifunctional.
· “Pin#” Pin number on the carrier board interface connector · “Type”
Signal type, see the definition of different signal types below ·
“Description” Signal description with regards to the interface in question ·
“Voltage Domain” Voltage level of the particular signal · “Availability”
Depending on UCM-iMX93 configuration options, certain carrier board
interface pins are physically disconnected (floating). The “Availability”
column summarizes configuration requirements for each signal. All the listed
requirements must be met (logical AND) for a signal to be “available” unless
noted otherwise.
Each described signal can be one of the following types. Signal type is noted
in the “Signal description” tables. Multifunctional pin direction, pull
resistor, and open drain functionality is software controlled. The “Type”
column header for multifunctional pins refers to the recommended pin
configuration with regards to the discussed signal.
· “AI” Analog Input · “AO” Analog Output · “AIO” Analog Input/Output ·
“AP” Analog Power Output · “I” Digital Input · “O” Digital Output · “IO”
Digital Input/Output · “P” Power · “PD” – Always pulled down onboard UCM-
iMX93, followed by pull value. · “PU” – Always pulled up onboard UCM-iMX93,
followed by pull value. · “LVDS” – Low-voltage differential signaling.
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Peripheral Interfaces
4.1
4.1.1
4.1.2
Display Interfaces
MIPI-DSI
The UCM-iMX93 MIPI-DSI interface is derived from the four-lane MIPI display
interface available on the i.MX93 SoC. The following main features are
supported:
· Compliant with MIPI DSI specification v1.2 and MIPI D-PHY specification v1.2
· Maximum data rate per lane of 1.5 Gbps · Maximum resolution ranges up to
1920 x 1200 p60
The following table below summarizes the MIPI-DSI interface signals.
Table 5 MIPI-DSI Interface Signals
Signal Name
Pin #
Type
Description
DSI_CKN
P2-21
AO Negative part of MIPI-DSI clock diff-pair
DSI_CKP
P2-23
AO Positive part of MIPI-DSI clock diff-pair
DSI_DN0
P2-1
AO Negative part of MIPI-DSI data diff-pair 0
DSI_DP0
P2-2
AO Positive part of MIPI-DSI data diff-pair 0
DSI_DN1
P2-15
AO Negative part of MIPI-DSI data diff-pair 1
DSI_DP1
P2-17
AO Positive part of MIPI-DSI data diff-pair 1
DSI_DN2
P2-5
AO Negative part of MIPI-DSI data diff-pair 2
DSI_DP2
P2-7
AO Positive part of MIPI-DSI data diff-pair 2
DSI_DN3
P2-11
AO Negative part of MIPI-DSI data diff-pair 3
DSI_DP3
P2-13
AO Positive part of MIPI-DSI data diff-pair 3
Availability Always Always Always Always Always Always Always Always Always Always
LVDS Interface
UCM-iMX93 provides one LVDS interface derived from the i.MX93 LVDS display
bridge. It supports the following key features:
· Single channel (4 lanes) output at up to 80MHz pixel clock · Resolutions of
up to 1366 x 768 p60 or 1280 x 800 p60
The table below summarizes the LVDS interface signals.
Table 6 LVDS Interface Signals
Signal Name Pin # Type
Description
LVDS_CLK_N
P2-14
AO Negative part of LVDS clock diff-pair
LVDS_CLK_P
P2-12
AO Positive part of LVDS clock diff-pair
LVDS_D0_N
P2-26
AO Negative part of LVDS data diff-pair 0
LVDS_D0_P
P2-24
AO Positive part of LVDS data diff-pair 0
LVDS_D1_N
P2-20
AO Negative part of LVDS data diff-pair 1
LVDS_D1_P
P2-18
AO Positive part of LVDS data diff-pair 1
LVDS_D2_N
P2-8
AO Negative part of LVDS data diff-pair 2
LVDS_D2_P
P2-6
AO Positive part of LVDS data diff-pair 2
LVDS_D3_N
P2-4
AO Negative part of LVDS data diff-pair 3
LVDS_D3_P
P2-2
AO Positive part of LVDS data diff-pair 3
Availability
Always Always Always Always Always Always Always Always Always Always
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Peripheral Interfaces
4.2
4.3
4.3.1
Camera Interface
UCM-iMX93 provides one MIPI-CSI interface, derived from the MIPI CSI host
controller integrated into the i.MX93 SoC. The controller supports the
following main features:
· Up to two data lanes and one clock lane · Complaint with MIPI CSI-2
specification v1.3 and MIPI D-PHY specification v1.2
Please refer to the i.MX93 Reference manual for additional details. The
following table summarizes MIPI-CSI signals.
Table 7 MIPI-CSI Interface Signals
Signal Name
Pin # Type
Description
Availability
MIPI_CSI _CLK_N MIPI_CSI _CLK_P MIPI_CSI_D0_N MIPI_CSI_D0_P MIPI_CSI_D1_N MIPI_CSI_D1_P
P2-30 P2-32 P2-31 P2-33 P2-35 P2-37
AI Negative part of MIPI-CSI1 clock diff-pair AI Positive part of MIPI-CSI1 clock diff-pair AI Negative part of MIPI-CSI1 data diff-pair 0 AI Positive part of MIPI-CSI1 data diff-pair 0 AI Negative part of MIPI-CSI11 data diff- pair 1 AI Positive part of MIPI-CSI1 data diff-pair 1
Always Always Always Always Always Always
Audio Interfaces
S/PDIF
UCM-iMX93 provides one S/PDIF transmitter with one output and one S/PDIF
receiver with one input.
Please refer to the i.MX93 Reference manual for additional details. The
following table summarizes the S/PDIF interface signals.
Table 8 S/PDIF Interface Signals
Signal Name Pin # Type
Description
SPDIF_IN SPDIF_OUT
P1-79 P2-43 P2-47 P1-81 P2-47
I SPDIF input data line signal O SPDIF output data line signal
Voltage Domain
3.3V 1.8V 1.8V 3.3V 1.8V
Availability Always Always
NOTE: S/PDIF signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
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Peripheral Interfaces
4.3.2
SAI
UCM-iMX93 supports up-to two of the i.MX93 integrated synchronous audio
interface (SAI) modules. The SAI module provides a synchronous audio interface
(SAI) that supports full duplex serial interfaces with frame synchronization,
such as I2S, AC97, TDM, and codec/DSP interfaces. The following main features
are supported:
· One transmitter with independent bit clock and frame sync supporting 1 data
line. One
receiver with independent bit clock and frame sync supporting 1 data line.
· Maximum Frame Size of 32 words. · Word size of between 8-bits and 32-bits.
Separate word size configuration for the first
word and remaining words in the frame.
· Asynchronous 32 × 32-bit FIFO for each transmit and receive channel
Please refer to the i.MX93 Reference manual for additional details. The tables
below summarize the SAI interface signals.
Table 9 SAI1 Signals
Signal Name
Pin # Type
Description
SAI1_MCLK SAI1_RX_DATA[0] SAI1_TX_DATA[0] SAI1_TX_DATA[1] SAI1_TX_BCLK
SAI1_TX_SYNC
P1-19 P1-45 P1-45 P1-53 P1-87 P1-51
P1-87
Audio master clock. An input when IO generated externally and an output when
generated internally.
I
Receive data, sampled synchronously by the bit clock
O
Transmit data signal synchronous to bit clock.
O
Transmit data signal synchronous to bit clock.
Transmit bit clock. An input when
O generated externally and an output when
generated internally.
Transmit frame sync. An input sampled by
O
bit clock when generated externally. A bit clock synchronous output when generated
internally.
Voltage Domain
3.3V 3.3V 3.3V 3.3V 3.3V
3.3V
3.3V
Availability Always Always Always Always Always Always
Always
NOTE: SAI1 signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
Table 10 SAI2 Signals
Signal Name
SAI2_MCLK SAI2_RX_DATA[0] SAI2_RX_DATA[1] SAI2_RX_DATA[2] SAI2_RX_DATA[3]
SAI2_RX_BCLK
Pin #
P2-45 P2-63 P2-65 P2-61 P2-59 P2-70
Type
Description
Audio master clock. An input when
IO generated externally and an output when
generated internally.
I
Receive data, sampled synchronously by the bit clock
I
Receive data, sampled synchronously by the bit clock
I
Receive data, sampled synchronously by the bit clock
I
Receive data, sampled synchronously by the bit clock
Receive bit clock. An input when
I generated externally and an output when
generated internally.
Voltage Domain
1.8V
1.8V 1.8V 1.8V 1.8V
1.8V
Availability
Always Always Always Always Always Always
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Peripheral Interfaces
4.3.3
Signal Name
SAI2_RX_SYNC SAI2_TX_DATA[0] SAI2_TX_DATA[1] SAI2_TX_DATA[2] SAI2_TX_DATA[3]
SAI2_TX_BCLK
SAI2_TX_SYNC
Pin #
P2-68 P2-53 P2-55 P2-41 P2-43 P2-69
P2-67
Type
Description
Receive frame sync. An input sampled by
I
bit clock when generated externally. A bit clock synchronous output when generated
internally.
O
Transmit data signal synchronous to bit clock.
O
Transmit data signal synchronous to bit clock.
O
Transmit data signal synchronous to bit clock.
O
Transmit data signal synchronous to bit clock.
Transmit bit clock. An input when
O generated externally and an output when
generated internally.
Transmit frame sync. An input sampled by
O
bit clock when generated externally. A bit clock synchronous output when generated
internally.
Voltage Domain
1.8V
1.8V 1.8V 1.8V 1.8V 1.8V
1.8V
Availability
Always Always Always Always Always Always
Always
NOTE: SAI2 signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
MQS
UCM-iMX93 supports up-to two MOQ interfaces that can be used to generate
medium quality audio via standard GPIO.
Please refer to the i.MX93 Reference manual for additional details. The
following table summarizes the S/PDIF interface signals.
Table 11 MQS Signals
Signal Name
Pin # Type
Description
MQS1_LEFT MQS1_RIGHT MQS2_LEFT MQS2_RIGHT
P1-21 P1-87 P1-23 P1-45 P1-71 P2-47 P1-67 P2-45
O Left signal output O Right signal output O Left signal output O Right signal output
Voltage Domain
3.3V 3.3V 3.3V 3.3V 1.8 1.8 1.8 1.8
Availability
Always Always Always Always Always Always Always Always
NOTE: MQS signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
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Peripheral Interfaces
4.4
4.4.1
Ethernet
Gigabit Ethernet
UCM-iMX93 incorporates an optional (“E” configuration option) full-featured
10/100/1000 Ethernet interface implemented with Realtek RTL8211E GbE PHY.
The following main features are supported:
· 10/100/1000 BASE-T IEEE 802.3 compliant · IEEE 802.3u compliant Auto-
Negotiation · Supports all IEEE 1588 frames – inside the MAC · Automatic
channel swap (ACS) · Automatic MDI/MDIX crossover · Automatic polarity
correction · Activity and speed indicator LED controls
The table below summarizes the GbE interface signals.
Table 12 GbE Interface Signals
Signal Name
Pin #
Type
ETH0_LED_ACT
P2-83
ETH0_LINK-LED_10_100
P2-86
ETH0_LINK-LED_1000
ETH0_MDI0N ETH0_MDI0P ETH0_MDI1N ETH0_MDI1P ETH0_MDI2N ETH0_MDI2P ETH0_MDI3N
ETH0_MDI3P
P2-75
P2-73
AIO
P2-74
AIO
P2-80
AIO
P2-78
AIO
P2-81
AIO
P2-79
AIO
P2-85
AIO
P2-84
AIO
Description Active High, activity LED driver. 3.3V signal, PHY strap Active
High, link, any speed LED driver. 3.3V signal Active High, link, any speed ,
blinking on transmit or receive PHY strap Negative part of 100ohm diff-pair 0
Positive part of 100ohm diff-pair 0
Negative part of 100ohm diff-pair 1
Positive part of 100ohm diff-pair 1
Negative part of 100ohm diff-pair 2
Positive part of 100ohm diff-pair 2
Negative part of 100ohm diff-pair 3
Positive part of 100ohm diff-pair 3
Availability With ‘E’ option
With ‘E’ option
With ‘E’ option
With ‘E’ option With ‘E’ option With ‘E’ option With ‘E’ option With ‘E’
option With ‘E’ option With ‘E’ option With ‘E’ option
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Peripheral Interfaces
4.4.2
RGMII
UCM-iMX93 features up-to two RMGII interfaces. Primary RGMII interface ENET1
is available only when UCM-iMX93 is assembled without the “E” configuration
option.
Secondary RGMII interface ENET2 is available with all UCM-iMX93
configurations.
The tables below summarize the Ethernet RGMII interface signals.
Table 13 Primary RGMII ENET1 (QOS) Interface Signals
Signal Name
ENET1_MDC
ENET1_MDIO
ENET1_RD0 ENET1_RD1 ENET1_RD2 ENET1_RD3
ENET1_RX_CTL
ENET1_RXC ENET1_TD0 ENET1_TD1 ENET1_TD2 ENET1_TD3 ENET1_TXC
ENET1_TX_CTL ENET11588 EVENT0_IN ENET11588 EVENT0_OUT
Pin # Type
Description
P2-60 P2-62 P2-86
O
Provides a timing reference to the PHY for data transfers on the MDIO signal
Transfers control information between the
IO
external PHY and the MAC. Data is synchronous to MDC. This signal is an input
after reset
I Ethernet input data from the PHY
P2-83
I Ethernet input data from the PHY
P2-84
I Ethernet input data from the PHY
P2-85 P2-81 P2-78 P2-75
I Ethernet input data from the PHY
Contains RX_EN on the rising edge of
I RGMII_RXC, and RX_EN XOR RX_ER on the
falling edge of RGMII_RXC (RGMII mode)
I
Timing reference for RX_DATA[3:0] and RX_CTL in RGMII MODE
O Ethernet output data to PHY
P2-80 O Ethernet output data to PHY
P2-77 O Ethernet output data to PHY
P2-74 P2-79 P2-73 P2-92
O Ethernet output data to PHY
O
Timing reference for TX_DATA[3:0] and TX_CTL in RGMII MODE
Contains TX_EN on the rising edge of
O RGMII_TXC, and TX_EN XOR TX_ER on the
falling edge of RGMII_TXC (RGMII mode)
I 1588 event input
P2-96 O 1588 event output
Voltage Domain
1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V
1.8V
1.8V 1.8V 1.8V 1.8V 1.8V 1.8V
1.8V
Availability
Only w/o ‘E’ option Only w/o ‘E’ option Only w/o ‘E’ option Only w/o ‘E’
option Only w/o ‘E’ option Only w/o ‘E’ option Only w/o ‘E’ option
Only w/o ‘E’ option
Only w/o ‘E’ option Only w/o ‘E’ option Only w/o ‘E’ option Only w/o ‘E’
option Only w/o ‘E’ option Only w/o ‘E’ option
Only w/o ‘E’ option
3.3V/1.8V
Always
3.3V/1.8V
Always
NOTE: RGMII ENET1 interface operates at 1.8V voltage level.
NOTE: ENET1 signals are multiplexed with other functions. For additional
details please refer to chapter 5.6 of this document.
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Peripheral Interfaces
Table 14 Secondary RGMII ENET2 Interface Signals
Signal Name
ENET2_MDC
ENET2_MDIO
ENET2_RD0 ENET2_RD1 ENET2_RD2 ENET2_RD3
ENET2_RX_CTL
ENET2_RXC ENET2_TD0 ENET2_TD1 ENET2_TD2 ENET2_TD3
ENET2_TXC
ENET2_TX_CTL ENET21588 EVENT0_IN ENET21588 EVENT0_OUT ENET21588
EVENT1_OUT
Pin #
P2-68
P2-70
P2-41 P2-43 P2-45 P2-47 P2-53
P2-55 P2-59 P2-61 P2-65 P2-63 P2-69
P2-67
P2-99 P2-97 P2-94
Type
Description
O
Provides a timing reference to the PHY for data transfers on the MDIO signal
Transfers control information between
IO
the external PHY and the MAC. Data is synchronous to MDC. This signal is an
input after reset
I
Ethernet input data from the PHY
I
Ethernet input data from the PHY
I
Ethernet input data from the PHY
I
Ethernet input data from the PHY
Contains RX_EN on the rising edge of
I
RGMII_RXC, and RX_EN XOR RX_ER on the
falling edge of RGMII_RXC (RGMII mode)
I
Timing reference for RX_DATA[3:0] and RX_CTL in RGMII MODE
O
Ethernet output data to PHY
O
Ethernet output data to PHY
O
Ethernet output data to PHY
O
Ethernet output data to PHY
O
Timing reference for TX_DATA[3:0] and TX_CTL in RGMII MODE
Contains TX_EN on the rising edge of
O
RGMII_TXC, and TX_EN XOR TX_ER on the
falling edge of RGMII_TXC (RGMII mode)
I
1588 event input
O
1588 event output
O
1588 event output
Voltage Domain
1.8V
1.8V
1.8V 1.8V 1.8V 1.8V 1.8V
1.8V 1.8V 1.8V 1.8V 1.8V 1.8V
1.8V
3.3V/1.8V 3.3V/1.8V 3.3V/1.8V
Availability
Always
Always
Always Always Always Always Always
Always Always Always Always Always Always
Always
Always Always Always
NOTE: RGMII ENET2 signals operate at 1.8V voltage level.
NOTE: ENET2 signals are multiplexed with other functions. For additional
details please refer to chapter 5.6 of this document.
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4.5 4.6
Peripheral Interfaces
WiFi and Bluetooth Interfaces
UCM-iMX93 features optional 802.11ac WiFi and Bluetooth functions implemented
with the AzureWave AW-CM276NF certified WiFi module (NXP 88W8997 chipset).
AzureWave AW-CM276NF provides the following key features:
· IEEE 802.11 ac/a/b/g/n, Wi-Fi compliant · IEEE 802.11i for advanced security
· Multiple power saving modes for low power consumption · Quality of Service
(QoS) support · Bluetooth 5.3 complaint
The wireless module is interfaced with i.MX93 SoC through SDIO3 interface.
The wireless module provides two on-board MHF4 antenna connectors:
· ANT_A main WiFi antenna · ANT_B auxiliary WiFi / Bluetooth antenna
NOTE: WiFi and Bluetooth functions are available only with “WB” configuration
option.
USB
UCM-iMX93 provides two dual-role USB2.0 ports. USB port #1 can be configured
as host or device, while the second port is configured permanently for host
mode.
Please refer to the i.MX93 Reference manual for additional details.
The tables below summarize the USB interface signals.
Table 15 USB port #1 Signals
Signal Name
Pin # Type
USB1_DN
P1-14 IO
USB1_DP
P1-12 IO
USB1_VBUS_DET
P1-24
I
USB1_ID
P1-22
I
Description USB2.0 negative data USB2.0 positive data USB1 VBUS detect USB1 ID
Availability Always Always Always Always
Table 16 USB port #2 Signals
Signal Name
Pin # Type
USB2_DN
P1-5 IO
USB2_DP
P1-3 IO
USB2_VBUS_DET
P1-1
I
USB2_ID
P1-7
I
Description USB2.0 negative data USB2.0 positive data USB2 VBUS detect USB2 ID
Availability Always Always Always Always
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4.7
Peripheral Interfaces
MMC / SD /SDIO
UCM-iMX93 features two SD/SDIO ports. These ports are derived from the i.MX93
uSDHC2 and uSDHC3 controllers. uSDHC IP supports the following main features:
· Fully compliant with MMC 5.1 command/response sets and physical layer ·
Fully compliant with SD 3.0 command/response sets and physical layer
Please refer to the i.MX93 Reference manual for additional details.
The table below summarizes the MMC/SD/SDIO interface signals.
Table 17 SD2 Signals
Signal Name
Pin # Type
Description
SD2_CLK SD2_CMD SD2_DATA0 SD2_DATA1 SD2_DATA2
SD2_DATA3
SD2_RESET_B
P2-96 P2-100 P2-97 P2-99 P2-94
P2-98
P2-51
O Clock for MMC/SD/SDIO card
IO CMD line connect to card
IO
DATA0 line in all modes. Also used to detect busy state
IO
DATA1 line in 4/8-bit mode. Also used to detect interrupt in 1/4- bit mode
IO
DATA2 line or Read Wait in 4-bit mode. Read Wait in 1-bit mode
DATA3 line in 4/8-bit mode or configured
IO as card detection pin. May be configured as
card detection pin in 1-bit mode.
O Card hardware reset signal, active LOW
Voltage Domain 3.3V/1.8V 3.3V/1.8V 3.3V/1.8V 3.3V/1.8V 3.3V/1.8V
3.3V/1.8V
3.3V/1.8V
Availability Always Always Always Always Always
Always
Always
SD2_CD_B
P2-92
I Card detection pin
3.3V/1.8V
Always
NOTE: SD2 pins can be configured to operate at 3.3V or 1.8V voltage levels.
Voltage level is controlled by SoC pin SD2_VSELECT.
NOTE: SD2 signals are multiplexed with other functions. For additional details
please refer to chapter 5.6 of this document.
Table 18 SD3 Signals
Signal Name
Pin # Type
Description
SD3_CLK
P2-36 O Clock for MMC/SD/SDIO card
SD3_CMD SD3_DATA0 SD3_DATA1 SD3_DATA2 SD3_DATA3
P2-38 IO CMD line connect to card
P2-42
IO
DATA0 line in all modes. Also used to detect busy state
P2-44
IO
DATA1 line in 4/8-bit mode. Also used to detect interrupt in 1/4- bit mode
P2-48
IO
DATA2 line or Read Wait in 4-bit mode. Read Wait in 1-bit mode
DATA3 line in 4/8-bit mode or configured as
P2-50 IO card detection pin. May be configured as card
detection pin in 1-bit mode.
Voltage Domain
1.8V
1.8V 1.8V 1.8V 1.8V 1.8V
Availability
Only w/o ‘WB’ option
Only w/o ‘WB’ option
Only w/o ‘WB’ option
Only w/o ‘WB’ option
Only w/o ‘WB’ option
Only w/o ‘WB’ option
NOTE: SD3 signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
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4.8
Peripheral Interfaces
FlexSPI
UCM-iMX93 provides one FlexSPI port that can support 4-bit serial flash memory
or serial RAM devices. Please refer to the i.MX93 Reference manual for
additional details.
The table below summarizes the FlexSPI interface signals.
Table 19 FlexSPI Signals
Signal Name
Pin # Type
Description
FLEXSPI_SCLK FLEXSPI _SS0 FLEXSPI _DATA[0] FLEXSPI _DATA[1] FLEXSPI _DATA[2] FLEXSPI _DATA[3]
P2-36 P2-38 P2-42 P2-44 P2-48 P2-50
O Flash serial clock O Flash chip select IO Flash data 0 IO Flash data 1 IO Flash data 2 IO Flash data 3
Voltage Domain
1.8V 1.8V 1.8V 1.8V 1.8V 1.8V
Availability
Only w/o ‘WB’ option
Only w/o ‘WB’ option
Only w/o ‘WB’ option
Only w/o ‘WB’ option
Only w/o ‘WB’ option
Only w/o ‘WB’ option
NOTE: FlexSPI signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
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4.9
Peripheral Interfaces
UART
UCM-iMX93 features up-to seven UART ports. The i.MX93 UART supports the
following features:
· 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd or
none). · Programmable baud rates up to 5 Mbps. · Hardware flow control support
for a request to send and clear to send signals.
NOTE: By default UART1 is assigned to be used as the main system console port.
NOTE: By default UART2 is assigned to be used as the M7 core debug port.
Please refer to the i.MX93 Reference manual for additional details. The tables below summarize the UART interface signals. Table 20 UART1 Signals
Signal Name
Pin # Type
Description
UART1_CTS UART1_RTS UART1_DTR UART1_DSR UART1_RXD UART1_TXD
P1-19 P1-72 P1-53 P1-51 P1-76 P1-74
O Clear to send I Request to send I Data terminal ready O Data set ready I Serial data receive O Serial data transmit
Voltage Domain
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
Availability
Always Always Always Always Always Always
NOTE: UART1 signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
Table 21 UART2 Signals
Signal Name
Pin # Type
Description
UART2_CTS UART2_RTS UART2_DTR UART2_DSR UART2_RXD UART2_TXD
P1-51 P1-53 P1-87 P1-45 P1-19 P1-72
O Clear to send I Request to send I Data terminal ready O Data set ready I Serial data receive O Serial data transmit
Voltage Domain
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
Availability
Always Always Always Always Always Always
NOTE: UART2 signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
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Peripheral Interfaces
Table 22 UART3 Signals
Signal Name
Pin # Type
Description
UART3_CTS
UART3_RTS UART3_DTR UART3_DSR UART3_RIN UART3_RXD
UART3_TXD
P1-96 P2-83 P1-95 P2-80 P2-73 P2-81 P2-62 P1-60 P2-86 P2-76 P2-75
O Clear to send
I Request to send I Data terminal ready O Data set ready I Ring indicator I
Serial data receive
O Serial data transmit
Voltage Domain
3.3V 1.8V 3.3V 1.8V 1.8V 1.8V 1.8V 3.3V 1.8V 3.3V 1.8V
Availability
Only w/o ‘WB’ option
Only w/o ‘E’ option Only w/o ‘WB’ option Only w/o ‘E’ option Only w/o ‘E’
option Only w/o ‘E’ option Only w/o ‘E’ option Only w/o ‘WB’ option Only w/o
‘E’ option Only w/o ‘WB’ option Only w/o ‘E’ option
NOTE: UART3 signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
Table 23 UART4 Signals
Signal Name
Pin # Type
Description
UART4_RXD
UART4_TXD UART4_CTS UART4_RTS UART4_DTR UART4_DSR UART4_RIN
P1-60 P2-41 P2-76 P2-59 P1-96 P2-45 P1-95 P2-61 P2-67
P2-53
P2-70
I Serial data receive
O Serial data transmit O Clear to send I Request to send I Data terminal ready
O Data set ready I Ring indicator
Voltage Domain
3.3V 1.8V 3.3V 1.8V 3.3V 1.8V 3.3V 1.8V 1.8V
Availability
Only w/o ‘WB’ option
Always Only w/o ‘WB’ option Always Only w/o ‘WB’ option Always Only w/o ‘WB’
option Always
Always
1.8V
Always
1.8V
Always
NOTE: UART4 signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
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Peripheral Interfaces
Table 24 UART5 Signals
Signal Name
Pin # Type
Description
UART5_RXD UART5_TXD UART5_CTS UART5_RTS
P1-26 P1-71 P1-28 P1-67 P1-30 P1-73 P1-32 P1-65
I UART-5 serial data receive O UART-5 serial data transmit O UART-5 clear to send I UART-5 request to send
Voltage Domain
3.3V 1.8V 3.3V 1.8V 3.3V 1.8V 3.3V 1.8V
Availability
Only w/o ‘WB’ option
Always Only w/o ‘WB’ option Always Only w/o ‘WB’ option Always Only w/o ‘WB’
option Always
NOTE: UART5 signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
Table 25 UART6 Signals
Signal Name
Pin # Type
Description
UART6_RXD UART6_TXD UART6_CTS UART6_RTS
P2-56 P2-58 P2-52 P1-98
I Serial data receive O Serial data transmit O Clear to send I Request to send
Voltage Domain
3.3V 3.3V 3.3V 3.3V
Availability
Only w/o ‘E’ option Only w/o ‘E’ option Only w/o ‘E’ option Only w/o ‘WB’
option
NOTE: UART6 signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
Table 26 UART7 Signals
Signal Name
Pin # Type
Description
UART7_RXD UART7_TXD UART7_CTS UART7_RTS
P1-41 P1-39 P1-35 P1-37
I Serial data receive O Serial data transmit O Clear to send I Request to send
Voltage Domain
3.3V 3.3V 3.3V 3.3V
Availability
Always Always Always Always
NOTE: UART7 signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
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Peripheral Interfaces
4.10
CAN-FD
UCM-iMX93 features up-to two CAN-FD interfaces. These interfaces support the
following key features:
· Full implementation of the CAN FD protocol and CAN protocol specification
version 2.0B · Compliant with the ISO 11898-1 standard
Please refer to the i.MX93 Reference manual for additional details.
The tables below summarize the CAN interface signals.
Table 27 CAN1 Signals
Signal Name
Pin # Type
Description
CAN1_TX CAN1_RX
P1-21 P1-53 P1-23 P1-51
O CAN transmit pin I CAN receive pin
Voltage Domain
3.3V 3.3V 3.3V 3.3V
Availability Always Always
Table 28 CAN2 Signals
Signal Name
Pin # Type
Description
CAN2_TX CAN2_RX
P1-33 P1-71 P2-74 P2-97 P1-49 P1-67 P2-77 P2-99
O CAN transmit pin I CAN receive pin
Voltage Domain
3.3V 1.8V 1.8V 3.3V/1.8V 3.3V 1.8V 1.8V 3.3V/1.8V
Availability
Always Always Only w/o ‘E’ option Always Always Always Only w/o ‘E’ option
Always
NOTE: CAN signals are multiplexed with other functions. For additional details
please refer to chapter 5.6 of this document.
NOTE: Pins denoted “3.3V/1.8V” can be configured to operate at 3.3V or 1.8V
voltage levels. Voltage level is controlled by SoC pin SD2_VSELECT.
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Peripheral Interfaces
4.11
SPI
Up-to seven SPI interfaces are accessible through the UCM-iMX93 carrier board
interface. The SPI interfaces are derived from i.MX93 integrated low-power SPI
modules. The following key features are supported:
· Full-duplex synchronous serial interface · Master/Slave configurable · One
Chip Select (SS) signal · Direct Memory Access (DMA) support
Please refer to the i.MX93 Reference manual for additional details.
SPI1 and SPI2 channels are limited to maximum frequency of 10MHz.
The following tables summarize the SPI interface signals.
Table 29 SPI1 Signals
Signal Name
Pin # Type
Description
SPI1_SIN SPI1_SOUT SPI1_SCLK SPI1_PCS0 SPI1_PCS1
P1-51 P1-45 P1-53 P1-87 P1-23
I Serial data input O Master data out; slave data in O Master clock out; slave clock in O Chip select 0 O Chip select 1
Voltage Domain
3.3V 3.3V 3.3V 3.3V 3.3V
Availability
Always Always Always Always Always
NOTE: SPI1 maximum frequency is limited to 10MHz.
Table 30 SPI2 Signals
Signal Name
Pin # Type
Description
SPI2_SIN SPI2_SOUT SPI2_SCLK SPI2_PCS0
P1-76 P1-19 P1-72 P1-74
I Master data in; slave data out O Master data out; slave data in O Master clock out; slave clock in O Chip select 0
Voltage Domain
3.3V 3.3V 3.3V 3.3V
Availability
Always Always Always Always
NOTE: SPI2 maximum frequency is limited to 10MHz.
Table 31 SPI3 Signals
Signal Name
Pin # Type
Description
SPI3_SIN SPI3_SOUT SPI3_SCLK SPI3_PCS0 SPI3_PCS1
P1-41 P1-35 P1-37 P1-39 P1-98
I Master data in; slave data out O Master data out; slave data in O Master clock out; slave clock in O Chip select 0 O Chip select 1
Voltage Domain
3.3V 3.3V 3.3V 3.3V
3.3V
Availability
Always Always Always Always Only w/o ‘WB’ option
NOTE: SPI signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
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Peripheral Interfaces
Table 32 SPI4 Signals
Signal Name
Pin # Type
Description
SPI4_SIN SPI4_SOUT SPI4_SCLK SPI4_PCS0 SPI4_PCS1
SPI4_PCS2
P1-59 P1-61 P1-63 P1-89 P1-95
P1-96
I Master data in; slave data out O Master data out; slave data in O Master
clock out; slave clock in O Chip select 0 O Chip select 1
O Chip select 2
Table 33 SPI5 Signals
Signal Name
Pin # Type
Description
SPI5_SIN SPI5_SOUT SPI5_SCLK SPI5_PCS0 SPI5_PCS1
P1-59 P1-61 P1-63 P1-89 P1-49
I Master data in; slave data out O Master data out; slave data in O Master clock out; slave clock in O Chip select 0 O Chip select 1
Table 34 SPI6 Signals
Signal Name
Pin # Type
Description
SPI6_SIN SPI6_SOUT SPI6_SCLK SPI6_PCS0
P1-26 P1-30 P1-32 P1-28
I Master data in; slave data out O Master data out; slave data in O Master clock out; slave clock in O Chip select 0
Table 35 SPI7 Signals
Signal Name
Pin # Type
Description
SPI7_SIN SPI7_SOUT SPI7_SCLK SPI7_PCS0 SPI7_PCS1
P2-56 P2-52 P1-98 P2-58 P1-33
I Master data in; slave data out O Master data out; slave data in O Master clock out; slave clock in O Chip select 0 O Chip select 1
Voltage Domain
3.3V 3.3V 3.3V 3.3V 3.3V
3.3V
Availability
Always Always Always Always Only w/o ‘WB’ option Only w/o ‘WB’ option
Voltage Domain
3.3V 3.3V 3.3V 3.3V 3.3V
Availability
Always Always Always Always Always
Voltage Domain
3.3V 3.3V 3.3V 3.3V
Availability
Only w/o ‘WB’ option
Only w/o ‘WB’ option
Only w/o ‘WB’ option
Only w/o ‘WB’ option
Voltage Domain
3.3V 3.3V 3.3V 3.3V 3.3V
Availability
Only w/o ‘E’ option Only w/o ‘E’ option Only w/o ‘WB’ option Only w/o ‘E’
option
Always
NOTE: SPI signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
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Peripheral Interfaces
4.12
I2C
UCM-iMX93 features up-to six I2C bus interfaces. The following general
features are supported by all I2C bus interfaces:
· Compliant with Philips I2C specification version 2.1 · Supports standard
mode (up to 100K bits/s) and fast mode (up to 400K bits/s) · Multi-master
operation
Please refer to the i.MX93 Reference manual for additional details.
The tables below summarize the I2C interface signals.
Table 36 I2C3 Signals
Signal Name
Pin # Type
Description
I2C3_SCL I2C3_SDA
P1-26 P1-94 P1-28 P1-91
O I2C serial clock line IO I2C serial data line
Voltage Domain
3.3V 3.3V 3.3V 3.3V
Availability
Only w/o ‘WB’ option
Always Only w/o ‘WB’ option Always
Table 37 I2C4 Signals
Signal Name
Pin # Type
Description
I2C4_SCL I2C4_SDA
P1-32 P1-30
O I2C serial clock line IO I2C serial data line
Table 38 I2C5 Signals
Signal Name
Pin # Type
Description
I2C5_SCL I2C5_SDA
P1-26 P1-81 P1-28 P1-79
O I2C serial clock line IO I2C serial data line
Voltage Domain
3.3V
3.3V
Availability
Only w/o ‘WB’ option
Only w/o ‘WB’ option
Voltage Domain
3.3V 3.3V 3.3V 3.3V
Availability
Only w/o ‘WB’ option
Always Only w/o ‘WB’ option Always
Table 39 I2C6 Signals
Signal Name
Pin # Type
Description
I2C6_SCL I2C6_SDA
P1-32 P2-56 P1-30 P2-58
O I2C serial clock line IO I2C serial data line
Voltage Domain
3.3V 3.3V 3.3V 3.3V
Availability
Only w/o ‘WB’ option
Only w/o ‘E’ option Only w/o ‘WB’ option Only w/o ‘E’ option
NOTE: I2C signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
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Table 40 I2C7 Signals
Signal Name
Pin # Type
Description
I2C7_SCL I2C7_SDA
P1-41 P1-98 P1-39 P2-52
O I2C serial clock line IO I2C serial data line
Table 41 I2C8 Signals
Signal Name
Pin # Type
Description
I2C8_SCL I2C8_SDA
P1-100 P1-37 P1-35
O I2C serial clock line IO I2C serial data line
Voltage Domain
3.3V 3.3V 3.3V 3.3V
Availability
Always Only w/o ‘WB’ option Always Only w/o ‘E’ option
Voltage Domain
3.3V 3.3V 3.3V
Availability Always Always
NOTE: I2C signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
4.13
I3C
UCM-iMX93 supports one I3C bus interface. Please refer to the i.MX93 Reference manual for additional details. The tables below summarize the I3C interface signals.
Table 42 I3C2 Signals
Signal Name
Pin # Type
Description
I3C2_SCL I3C2_SDA I3C2_PUR
P2-60 P2-92
O Serial clock line
P2-62 P2-96
IO Serial data line
P2-80
Pull up resistance. There is internal pull-up resistance on SDA, which is controlled by
O the I3C controller. If the internal pullup is
P2-100
not enough, PUR can be used to control an external pull-up resistance on SDA actively.
Voltage Domain
1.8V 3.3V/1.8V
1.8V 3.3V/1.8V
1.8
Availability
Only w/o ‘E’ option Always Only w/o ‘E’ option Always
Only w/o ‘E’ option
3.3V/1.8V Always
NOTE: I3C signals are multiplexed with other functions. For additional details
please refer to chapter 5.6 of this document.
NOTE: Pins denoted “3.3V/1.8V” can be configured to operate at 3.3V or 1.8V
voltage levels. Voltage level is controlled by SoC pin SD2_VSELECT.
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Peripheral Interfaces
4.14
Timer/Pulse Width Modulation
i.MX93 supports multi-channel timer modules (TPM) that can be used for
electric motor control and power management. The timer modules support:
· Input capture · Output comparison · Generation of PWM signals
Please refer to the i.MX93 Reference manual for additional details.
The table below summarizes the PDM interface signals.
Table 43 TPM1 Signals
Signal Name
Pin # Type
Description
TPM1_EXTCLK TPM1_CH0 TPM1_CH2
P1-23 P1-76 P1-19
I External clock IO Channel 0 I/O pin IO Channel 2 I/O pin
Voltage Domain
3.3V 3.3V 3.3V
Availability
Always Always Always
Table 44 TPM3 Signals
Signal Name
Pin # Type
Description
TPM3_EXTCLK TPM3_CH0 TPM3_CH1
P1-41 P2-58 P1-61
I External clock IO Channel 0 I/O pin IO Channel 1 I/O pin
Voltage Domain
3.3V 3.3V 3.3V
Availability
Always Only w/o ‘E’ option Always
Table 45 TPM4 Signals
Signal Name
Pin # Type
Description
TPM4_EXTCLK TPM4_CH0 TPM4_CH1 TPM4_CH2 TPM4_CH3
P1-35 P2-56 P1-63 P1-100 P1-33
I External clock IO Channel 0 I/O pin IO Channel 1 I/O pin IO Channel 2 I/O pin IO Channel 3 I/O pin
Voltage Domain
3.3V
3.3V 3.3V 3.3V 3.3V
Availability
Always Only w/o ‘E’ option Always Always Always
Table 46 TPM5 Signals
Signal Name
Pin # Type
Description
TPM5_EXTCLK TPM5_CH0 TPM5_CH1 TPM5_CH2
P1-37 P2-52 P1-79 P1-89
I External clock IO Channel 0 I/O pin IO Channel 1 I/O pin IO Channel 2 I/O pin
Voltage Domain
3.3V 3.3V 3.3V 3.3V
Availability
Always Only w/o ‘E’ option Always Always
NOTE: TPM signals are multiplexed with other functions. For additional details please refer to chapter 5.6 of this document.
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Peripheral Interfaces
4.15 4.16 4.17
ADC
UCM-iMX93 features a 4-channel 12-bit ADC implemented in the i.MX93 SoC. Please refer to the i.MX93 Reference manual for additional details. The following table summarizes ADC signals.
Table 47 ADC Signals
Signal Name
Pin #
ADC_IN0
P2-89
ADC_IN1
P2-91
ADC_IN2
P2-93
ADC_IN3
P2-95
Type
Description
AI ADC input channel 0 AI ADC input channel 1 AI ADC input channel 2 AI ADC input channel 3
Availability Always Always Always Always
Tamper
i.MX93 supports two tamper pins two passive or one active. For additional details please refer to the i.MX93 Security Reference manual. The following table summarizes tamper signals.
Table 48 Tamper Signals
Signal Name
Pin # Type
TAMPER0
P2-25
IO
TAMPER1
P2-27
IO
Tamper channel 0 Tamper channel 1
Description
Availability Always Always
JTAG
UCM-iMX93 enables access to the i.MX93 JTAG port through the carrier board interface. Please refer to the i.MX93 Reference manual for additional details. The table below summarizes the JTAG interface signals.
Table 49 JTAG Interface Signals
Signal Name
Pin # Type
Description
JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS
P1-73 P1-71 P1-67 P1-65
I Test clock I Test data in O Test data out I Test mode select
Voltage Domain
1.8V 1.8V 1.8V 1.8V
Availability
Always Always Always Always
NOTE: JTAG interface operates at 1.8V voltage level.
4.18
GPIO
Up-to 79 of the i.MX93 general purpose input/output (GPIO) signals are
available through the UCM-iMX93 carrier board interface. In addition, GPIO
signals can produce interrupts. Please refer to the i.MX93 Reference manual
for additional details. The following table summarizes the GPIO interface
signals.
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Table 50 GPIO Signals
Signal Name
Pin # Type
Description
GPIO1_IO[4] GPIO1_IO[6] GPIO1_IO[8] GPIO1_IO[9] GPIO1_IO[12] GPIO1_IO[14] GPIO2_IO[0] GPIO2_IO[1] GPIO2_IO[2] GPIO2_IO[3] GPIO2_IO[4] GPIO2_IO[5] GPIO2_IO[6] GPIO2_IO[7] GPIO2_IO[8] GPIO2_IO[9] GPIO2_IO[10] GPIO2_IO[11] GPIO2_IO[13] GPIO2_IO[14] GPIO2_IO[15] GPIO2_IO[16] GPIO2_IO[17] GPIO2_IO[18] GPIO2_IO[19] GPIO2_IO[20] GPIO2_IO[21] GPIO2_IO[22] GPIO2_IO[23] GPIO2_IO[25] GPIO2_IO[27] GPIO2_IO[28] GPIO2_IO[29] GPIO3_IO[0] GPIO3_IO[1] GPIO3_IO[2] GPIO3_IO[3] GPIO3_IO[30] GPIO3_IO[31] GPIO3_IO[4] GPIO3_IO[5] GPIO3_IO[6] GPIO3_IO[7] GPIO3_IO[20]
P1-76 P1-19 P1-21 P1-23 P1-51 P1-45 P1-28 P1-26 P1-30 P1-32 P2-58 P2-56 P2-52 P1-98 P1-39 P1-41 P1-35 P1-37 P1-100 P2-76 P1-60 P1-96 P1-95 P1-89 P1-59 P1-61 P1-63 P1-79 P1-81 P1-33 P1-49 P1-91 P1-94 P2-92 P2-96 P2-100 P2-97 P1-73 P1-67 P2-99 P2-94 P2-98 P2-51 P2-36
IO General-purpose input/output IO General-purpose input/output IO General- purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General- purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General- purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General- purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General- purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General- purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output
Voltage Domain
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
3.3V 3.3V 3.3V 3.3V / 1.8V 3.3V / 1.8V 3.3V / 1.8V 3.3V / 1.8V 1.8V 1.8V 3.3V
/ 1.8V 3.3V / 1.8V 3.3V / 1.8V 3.3V / 1.8V 1.8V
Availability
Always Always Always Always Always Always Only w/o ‘WB’ option Only w/o ‘WB’
option Only w/o ‘WB’ option Only w/o ‘WB’ option Only w/o ‘E’ option Only w/o
‘E’ option Only w/o ‘E’ option Only w/o ‘WB’ option Always Always Always
Always Always Only w/o ‘WB’ option Only w/o ‘WB’ option Only w/o ‘WB’ option
Only w/o ‘WB’ option Always Always Always Always Always Always Always Always
Always Always Always Always Always Always Always Always Always Always Always
Always Only w/o ‘WB’ option
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GPIO3_IO[21] GPIO3_IO[22] GPIO3_IO[23] GPIO3_IO[24] GPIO3_IO[25] GPIO3_IO[28] GPIO3_IO[29] GPIO4_IO[0] GPIO4_IO[1] GPIO4_IO[2] GPIO4_IO[3] GPIO4_IO[4] GPIO4_IO[5] GPIO4_IO[6] GPIO4_IO[7] GPIO4_IO[8] GPIO4_IO[9] GPIO4_IO[10] GPIO4_IO[11] GPIO4_IO[12] GPIO4_IO[13] GPIO4_IO[14] GPIO4_IO[15] GPIO4_IO[16] GPIO4_IO[17] GPIO4_IO[18] GPIO4_IO[19] GPIO4_IO[20] GPIO4_IO[21] GPIO4_IO[22] GPIO4_IO[23] GPIO4_IO[24] GPIO4_IO[25] GPIO4_IO[26] GPIO4_IO[27]
P2-38 P2-42 P2-44 P2-48 P2-50 P1-71 P1-65 P2-60 P2-62 P2-74 P2-77 P2-80 P2-75 P2-73 P2-79 P2-81 P2-78 P2-86 P2-83 P2-84 P2-85 P2-68 P2-70 P2-63 P2-65 P2-61 P2-59 P2-67 P2-69 P2-53 P2-55 P2-41 P2-43 P2-45 P2-47
IO General-purpose input/output IO General-purpose input/output IO General- purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General- purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General- purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General- purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General- purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output IO General-purpose input/output
1.8V
Only w/o ‘WB’ option
1.8V
Only w/o ‘WB’ option
1.8V
Only w/o ‘WB’ option
1.8V
Only w/o ‘WB’ option
1.8V
Only w/o ‘WB’ option
1.8V
Always
1.8V
Always
1.8V
Only w/o ‘E’ option
1.8V
Only w/o ‘E’ option
1.8V
Only w/o ‘E’ option
1.8V
Only w/o ‘E’ option
1.8V
Only w/o ‘E’ option
1.8V
Only w/o ‘E’ option
1.8V
Only w/o ‘E’ option
1.8V
Only w/o ‘E’ option
1.8V
Only w/o ‘E’ option
1.8V
Only w/o ‘E’ option
1.8V
Only w/o ‘E’ option
1.8V
Only w/o ‘E’ option
1.8V
Only w/o ‘E’ option
1.8V
Only w/o ‘E’ option
1.8V
Always
1.8V
Always
1.8V
Always
1.8V
Always
1.8V
Always
1.8V
Always
1.8V
Always
1.8V
Always
1.8V
Always
1.8V
Always
1.8V
Always
1.8V
Always
1.8V
Always
1.8V
Always
NOTE: GPIO signals are multiplexed with other functions. For additional
details please refer to chapter 5.6 of this document.
NOTE: Pins denoted “3.3V/1.8V” can be configured to operate at 3.3V or 1.8V
voltage levels. Voltage level is controlled by SoC pin SD2_VSELECT.
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System Logic
5
5.1
5.2
5.3
5.3.1
SYSTEM LOGIC
Power Supply
Table 51 Power signals
Signal Name Connector #
Pin#
V_SOM
P1
11, 27, 43, 57, 69, 83
P2
9, 19, 29, 39, 57, 71, 87
VCC_RTC
P1
93
VSD_3V3 GND
P1
17
P1
4, 10, 20, 40, 54, 64, 78, 88
P2
10, 16, 22, 28, 34, 40, 46, 54, 72, 82
Type P P PO P
Description
Main power supply. Connect to a regulated DC supply or Li-Ion battery
RTC back-up battery power input. Connect to a 3V coin-cell lithium battery. If
RTC back-up is not required, connect this pin to GND. 3.3V regulator output.
Should be used to supply power to SD card connected to SD2 interface
Common ground
I/O Voltage Domains
UCM-iMX93 utilizes three separate I/O voltage domains that are used to power
different I/O modules of the i.MX93 SoC. Some pins operate at 3.3V, some at
1.8V. Voltage domain of each signal is specified in the peripheral interface
signals tables.
NOTE: Carrier-board designer must ensure that voltage level of the I/O pins matches the I/O voltage of the peripheral ICs on the carrier-board.
System and Miscellaneous Signals
Power management
UCM-iMX93 supports carrier board power supply control by means of two
dedicated output signals. Both signals are derived from the i.MX93 SoC. The
logic that controls both signals is supplied by the i.MX93 SoC SNVS power
rail.
The PMIC_STBY_REQ output can be used to signal the carrier board power supply
that UCM-iMX93 is in standby’ orOFF’ mode. Utilizing the external regulator
control signals enables carrier board power management functionality.
Please refer to the i.MX93 Reference manual for additional details. The table
below summarizes the external regulator control signals.
Table 52 External regulator control signals
Signal Name PMIC_STBY_REQ PMIC_ON_REQ ONOFF
Pin # P1-66 P1-68 P2-64
Type O O I
Description
When the processor enters SUSPEND mode, it will assert this signal. Active
high power-up request output from i.MX93 SoC. Pulled-Up Active low ON/OFF
signal (designed for an ONOFF switch).
Availability Always available Always available Always available
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5.4 5.5
System Logic
Reset
SYS_RST_PMIC signal is the main system reset input. Driving a valid logic zero invokes a global reset that affects every module on UCM-iMX93. Please refer to the i.MX93 Reference manual for additional details.
Table 53 Reset signals
Signal Name SYS_RST_PMIC
POR_B
Pin # P1-2 P2-66
Type I I
Description
Active Low cold reset input signal. Should be used as main system reset CPU
power on reset input pin, active low
Availability Always Always
Boot Sequence
UCM-iMX93 boot sequence defines which interface/media is used by UCM-iMX93 to
load and execute the initial software (such as SPL or/and U-boot). UCM-iMX93
can load initial software from the following interfaces/media:
· On-board primary boot device (eMMC with pre-flashed boot-loader) · An
external SD card using the SD2 interface · Serial Download boot using USB1
interface
UCM-iMX93 will query boot devices/interfaces for initial software in the order
defined by the active boot sequence. A total of three different boot sequences
are supported by UCM-iMX93:
· Standard sequence: designed for normal system operation with the on-board
primary
boot device as the boot media.
· Alternative sequence: designed to allow recovery from an external bootable
SD card in
case of data corruption of the on-board primary boot device. Using the
alternate sequence allows UCM-iMX93 to boot bypassing the onboard eMMC.
· Serial download mode: provides a means to download a program image to the
i.MX93
system-on-chip over USB serial connection
Logic values of boot selections signals define which of the supported boot
sequences is used by the system.
Table 54 Boot selection signals
Signal Name Pin # ALT_BOOT_SD P1-90 ALT_BOOT_USB P2-88
Type I I
Description
Active high alternate boot sequence select input. Leave floating or tie low
for standard boot sequence Active high alternate boot sequence select input.
Leave floating or tie low for standard boot sequence
Availability
Always available
Always available
Table 55 UCM-iMX93 boot sequences
Mode
ALT_BOOT_SD ALT_BOOT_USB
Booting sequence
Standard
Low or floating
Low or floating
Onboard eMMC (primary boot storage)
Alternative
High
Low or floating
SD card on SD/SDIO2 interface
SDP mode
Low or floating
High
Serial Downloader
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System Logic
5.6
Signal Multiplexing Characteristics
Up to 83 of the UCM-iMX93 carrier board interface pins are multifunctional. Multifunctional pins enable extensive functional flexibility of the UCM-iMX93 CoM/SoM by allowing usage of a single carrier board interface pin for one of several functions. Up-to 8 functions (MUX modes) are accessible through each multifunctional carrier board interface pin. The multifunctional capabilities of UCM-iMX93 pins are derived from the i.MX93 SoC control module.
NOTE: Pin function selection is controlled by software. NOTE: Each pin can be used for a single function at a time. NOTE: Only one pin can be used for each function (in case a function is available on more than one carrier board interface pin). NOTE: An empty MUX mode is a “RESERVED” function and must not be used.
Pin #
P1-19 P1-21 P1-23 P1-26 P1-28 P1-30 P1-32 P1-33 P1-35 P1-37 P1-39 P1-41 P1-45
Table 56 Multifunctional Signals
SoC Pin
Alt0
Alt1
Name
UART2_RXD
UART2_RX
UART1_RTS
PDM_CLK
PDM_CLK
MQS1_LEFT
PDM_BIT_STREAM0 PDM_BIT_STREAM[0]
MQS1_RIGHT
GPIO_IO01
GPIO2_IO[1]
I2C3_SCL
GPIO_IO00
GPIO2_IO[0]
I2C3_SDA
GPIO_IO02
GPIO2_IO[2]
I2C4_SDA
GPIO_IO03
GPIO2_IO[3]
I2C4_SCL
GPIO_IO25
GPIO2_IO[25]
GPIO_IO10
GPIO2_IO[10]
SPI3_SOUT
GPIO_IO11
GPIO2_IO[11]
SPI3_SCK
GPIO_IO08
GPIO2_IO[8]
SPI3_PCS0
GPIO_IO09
GPIO2_IO[9]
SPI3_SIN
SAI1_RXD0
SAI1_RX_DATA[0]
SAI1_MCLK
Alt2 SPI2_SOUT SPI1_PCS1
CAN2_TX
SPI1_SOUT
Alt3
Alt4
Alt5
TPM1_CH2 TPM1_EXTCLK
UART2_DSR
SAI1_MCLK
SPI6_SIN SPI6_PCS0 SPI6_SOUT SPI6_SCK TPM4_CH3 TPM4_EXTCLK TPM5_EXTCLK
TPM6_CH0 TPM3_EXTCLK MQS1_RIGHT
GPIO1_IO[6] GPIO1_IO[8] GPIO1_IO[9] UART5_RX UART5_TX UART5_RTS UART5_RTS
UART7_RTS UART7_RTS UART7_TX UART7_RX GPIO1_IO[14]
Alt6
CAN1_TX CAN1_RX I2C5_SCL I2C5_SDA I2C6_SDA I2C6_SCL SPI7_PCS1 I2C8_SDA
I2C8_SCL I2C7_SDA I2C7_SCL
Voltage Domain
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
Availability
Always Always Always not WB not WB not WB not WB Always Always Always Always
Always Always
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P1-49 P1-51 P1-53 P1-59 P1-60 P1-61 P1-63 P1-65 P1-67 P1-71 P1-72 P1-73 P1-74 P1-76 P1-79 P1-81 P1-87 P1-89 P1-91 P1-94 P1-95 P1-96 P1-98 P1-100 P2-36 P2-38 P2-41 P2-42 P2-43
GPIO_IO27 SAI1_TXC SAI1_TXD0 GPIO_IO19 GPIO_IO15 GPIO_IO20 GPIO_IO21 DAP_TMS_SWDIO DAP_TDO_TRACESWO DAP_TDI UART2_TXD DAP_TCLK_SWCLK UART1_TXD UART1_RXD GPIO_IO22 GPIO_IO23 SAI1_TXFS GPIO_IO18 GPIO_IO28 GPIO_IO29 GPIO_IO17 GPIO_IO16 GPIO_IO07 GPIO_IO13 SD3_CLK SD3_CMD ENET2_RD0 SD3_DATA0 ENET2_RD1
GPIO2_IO[27] SAI1_TX_BCLK SAI1_TX_DATA[0] GPIO2_IO[19] GPIO2_IO[15] GPIO2_IO[20] GPIO2_IO[21] JTAG_TMS JTAG_TDO JTAG_TDI UART2_TX JTAG_TCLK UART1_TX UART1_RX GPIO2_IO[22] GPIO2_IO[23] SAI1_TX_SYNC GPIO2_IO[18] GPIO2_IO[28] GPIO2_IO[29] GPIO2_IO[17] GPIO2_IO[16] GPIO2_IO[7] GPIO2_IO[13] SD3_CLK SD3_CMD ENET2_RD0 SD3_DATA0 ENET2_RD1
Revised October 2023
System Logic
UART2_RTS UART2_RTS UART3_RX
MQS2_RIGHT MQS2_LEFT UART1_RTS
SAI1_TX_DATA[1] I2C3_SDA I2C3_SCL
SPI3_PCS1 TPM4_CH2 FLEXSPI_SCLK FLEXSPI_SS0 UART4_RX FLEXSPI_DATA[0] SPDIF1_IN
CAN2_RX
TPM6_CH3
SPI5_PCS1
3.3V
Always
SPI1_SIN
UART1_DSR
CAN1_RX
GPIO1_IO[12]
3.3V
Always
SPI1_SCK
UART1_DTR
CAN1_TX
3.3V
Output only
PDM_BIT_STREAM[3]
SPI5_SIN
SPI4_SIN
TPM6_CH2
3.3V
Always
UART4_RX
3.3V
not WB
PDM_BIT_STREAM[0]
SPI5_SOUT
SPI4_SOUT
TPM3_CH1
3.3V
Always
PDM_CLK
SPI5_SCK
SPI4_SCK
TPM4_CH1
3.3V
Always
GPIO3_IO[29] UART5_RTS
1.8V
Always
CAN2_RX
GPIO3_IO[31]
UART5_TX
1.8V
Always
CAN2_TX
GPIO3_IO[28] UART5_RX
1.8V
Always
SPI2_SCK
3.3V
Output only
GPIO3_IO[30] UART5_RTS
1.8V
Always
SPI2_PCS0
3.3V
Output only
SPI2_SIN
TPM1_CH0
GPIO1_IO[4]
3.3V
Always
SPDIF1_IN
TPM5_CH1
TPM6_EXTCLK
I2C5_SDA
3.3V
Always
SPDIF1_OUT
TPM6_CH1
I2C5_SCL
3.3V
Always
SPI1_PCS0
UART2_DTR
MQS1_LEFT
3.3V
Output only
SPI5_PCS0
SPI4_PCS0
TPM5_CH2
3.3V
Always
3.3V
Always
3.3V
Always
UART3_RTS
SPI4_PCS1
UART4_RTS
3.3V
not WB
PDM_BIT_STREAM[2]
UART3_RTS
SPI4_PCS2
UART4_RTS
3.3V
not WB
SPI7_SCK
UART6_RTS
I2C7_SCL
3.3V
not WB
PDM_BIT_STREAM[3]
I2C8_SCL
3.3V
Always
GPIO3_IO[20]
1.8V
not WB
GPIO3_IO[21]
1.8V
not WB
SAI2_TX_DATA[2]
GPIO4_IO[24]
1.8V
Always
GPIO3_IO[22]
1.8V
not WB
SAI2_TX_DATA[3]
GPIO4_IO[25]
1.8V
Always
UCM-iMX93 Reference Guide
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P2-44 P2-45 P2-47 P2-48 P2-50 P2-51 P2-52 P2-53 P2-55 P2-56 P2-58 P2-59 P2-60 P2-61 P2-62 P2-63 P2-65 P2-67 P2-68 P2-69 P2-70 P2-73 P2-74 P2-75 P2-76 P2-77 P2-78 P2-79 P2-80
SD3_DATA1 ENET2_RD2 ENET2_RD3 SD3_DATA2 SD3_DATA3 SD2_RESET_B GPIO_IO06 ENET2_RX_CTL ENET2_RXC GPIO_IO05 GPIO_IO04 ENET2_TD0 ENET1_MDC ENET2_TD1 ENET1_MDIO ENET2_TD3 ENET2_TD2 ENET2_TX_CTL ENET2_MDC ENET2_TXC ENET2_MDIO ENET1_TX_CTL ENET1_TD3 ENET1_TD0 GPIO_IO14 ENET1_TD2 ENET1_RXC ENET1_TXC ENET1_TD1
Revised October 2023
SD3_DATA1 ENET2_RD2 ENET2_RD3 SD3_DATA2 SD3_DATA3 SD2_RESET GPIO2_IO[6] ENET2_RX_CTL ENET2_RXC GPIO2_IO[5] GPIO2_IO[4] ENET2_TD0 ENET1_MDC ENET2_TD1 ENET1_MDIO ENET2_TD3 ENET2_TD2 ENET2_TX_CTL ENET2_MDC ENET2_TXC ENET2_MDIO ENET1_TX_CTL ENET1_TD3 ENET1_TD0 GPIO2_IO[14] ENET1_TD2 ENET1_RXC ENET1_TXC ENET1_TD1
System Logic
FLEXSPI_DATA[1] UART4_RTS SPDIF1_OUT
FLEXSPI_DATA[2] FLEXSPI _DATA[3] TPM5_CH0 UART4_DSR
TPM4_CH0 TPM3_CH0 UART4_TX UART3_DCB UART4_RTS UART3_RIN
UART4_DTR UART4_DCB
UART4_RIN UART3_DTR
UART3_TX UART3_TX
UART3_RTS
SAI2_MCLK SPDIF1_IN
MQS2_RIGHT MQS2_LEFT
PDM_BIT_STREAM[1] SAI2_TX_DATA[0] SAI2_TX_DATA[1] PDM_BIT_STREAM[0] PDM_CLK
SAI2_RX_DATA[3] I3C2_SCL
SAI2_RX_DATA[2] I3C2_SDA
SAI2_RX_DATA[0] SAI2_RX_DATA[1] SAI2_TX_SYNC SAI2_RX_SYNC SAI2_TX_BCLK
SAI2_RX_BCLK
CAN2_TX
CAN2_RX
I3C2_PUR
SPI7_SOUT
SPI7_SIN SPI7_PCS0
GPIO3_IO[23] GPIO4_IO[26] GPIO4_IO[27] GPIO3_IO[24] GPIO3_IO[25] GPIO3_IO[7] UART6_RTS GPIO4_IO[22] GPIO4_IO[23] UART6_RX UART6_TX GPIO4_IO[19] GPIO4_IO[0] GPIO4_IO[18] GPIO4_IO[1] GPIO4_IO[16] GPIO4_IO[17] GPIO4_IO[20] GPIO4_IO[14] GPIO4_IO[21] GPIO4_IO[15] GPIO4_IO[6] GPIO4_IO[2] GPIO4_IO[5] GPIO4_IO[3] GPIO4_IO[9] GPIO4_IO[7] GPIO4_IO[4]
I2C7_SDA I2C6_SCL I2C6_SDA
UART4_TX
1.8V 1.8V 1.8V 1.8V 1.8V 3.3V/1.8V 3.3V 1.8V 1.8V 3.3V 3.3V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 3.3V 1.8V 1.8V 1.8V 1.8V
not WB Always Always not WB not WB Always not E Always Always not E not E Always not E Always not E Always Always Always Always Always Always not E not E not E not WB not E not E not E not E
UCM-iMX93 Reference Guide
38
P2-81 P2-83 P2-84 P2-85 P2-86 P2-92 P2-94 P2-96 P2-97 P2-98 P2-99 P2-100
ENET1_RX_CTL ENET1_RD1 ENET1_RD2 ENET1_RD3 ENET1_RD0 SD2_CD_B SD2_DATA2 SD2_CLK SD2_DATA0 SD2_DATA3 SD2_DATA1 SD2_CMD
ENET1_RX_CTL ENET1_RD1 ENET1_RD2 ENET1_RD3 ENET1_RD0 SD2_CD SD2_DATA2 SD2_CLK SD2_DATA0 SD2_DATA3 SD2_DATA1 SD2_CMD
UART3_DSR UART3_RTS
UART3_RX ENET1_1588_EVENT0_IN ENET2_1588_EVENT1_OUT ENET1_1588_EVENT0_OUT
ENET2_1588_EVENT0_OUT
ENET2_1588_EVENT1_IN ENET2_1588_EVENT0_IN
I3C2_SCL
I3C2_SDA CAN2_TX MQS2_LEFT CAN2_RX I3C2_PUR
GPIO4_IO[8] GPIO4_IO[11] GPIO4_IO[12] GPIO4_IO[13] GPIO4_IO[10] GPIO3_IO[0] GPIO3_IO[5] GPIO3_IO[1] GPIO3_IO[3] GPIO3_IO[6] GPIO3_IO[4] GPIO3_IO[2]
System Logic
1.8V 1.8V 1.8V 1.8V 1.8V 3.3V/1.8V 3.3V/1.8V 3.3V/1.8V 3.3V/1.8V 3.3V/1.8V 3.3V/1.8V 3.3V/1.8V
not E not E not E not E not E Always Always Always Always Always Always Always
Revised October 2023
UCM-iMX93 Reference Guide
39
System Logic
5.7
RTC
UCM-iMX93 features an on-board ultra-low-power AM1805 real time clock (RTC).
The RTC is connected to the i.MX93 SoC using I2C2 interface at address
0xD2/D3.
Back-up power supply is required in order to keep the RTC running and maintain
clock and time information when main supply is not present.
For more information about UCM-iMX93 RTC please refer to the AM1805 datasheet.
5.8
Reserved Pins
The following pins on UCM-iMX93 interface connectors are reserved and must be left unconnected.
Table 57 Reserved Signals
Connector #
Pin#
P1
25, 84, 92,97,99
P2
90
5.9
Not Connected Pins
The following pins on UCM-iMX93 interface connectors are unconnected.
Table 58 Unconnected Pins
Connector # P1 P2
Pin#
9, 13, 15, 29, 31, 34, 36, 38, 42, 44, 46, 47, 48, 50, 52, 55, 56, 62, 70, 77,
85, 86 49
Revised October 2023
UCM-iMX93 Reference Guide
40
6
6.1
Carrier board Interface
CARRIER BOARD INTERFACE
UCM-iMX93 carrier board interface uses two 100-pin carrier board connectors.
SoM pinout is detailed in the table below.
Connectors Pinout
Table 59 Connector P1
UCM-iMX93
Pin #
Ref.
Signal Name
2
SYS_RST_PMIC
5.4
4
GND
5.1
6
NC
5.9
8
NC
5.9
10
GND
5.1
12
USB1_DP
4.6
14
USB1_DN
4.6
16
NC
5.9
18
NC
5.9
20
GND
5.1
22
USB1_ID
4.6
24
USB1_VBUS_DET
4.6
GPIO2_IO[1]
4.18
I2C3_SCL
4.12
26
SPI6_SIN
4.11
UART5_RX
4.9
I2C5_SCL
4.12
GPIO2_IO[0]
4.18
I2C3_SDA
4.12
28
SPI6_PCS0
4.11
UART5_TX
4.9
I2C5_SDA
4.12
GPIO2_IO[2]
4.18
I2C4_SDA
4.12
30
SPI6_SOUT
4.11
UART5_RTS
4.9
I2C6_SDA
4.12
GPIO2_IO[3]
4.18
I2C4_SCL
4.12
32
SPI6_SCK
4.11
UART5_RTS
4.9
I2C6_SCL
4.12
34
NC
5.9
Pin #
1 3 5 7 9 11 13 15 17
19
21
23
25
27
29
31
33
UCM-iMX93 Signal Name
USB2_VBUS_DET USB2_DP USB2_DN USB2_ID NC V_SOM NC NC VSD_3V3 UART2_RX
UART1_RTS SPI2_SOUT TPM1_CH2 SAI1_MCLK
GPIO1_IO[6] MQS1_LEFT GPIO1_IO[8] CAN1_TX MQS1_RIGHT
SPI1_PCS1 TPM1_EXTCLK GPIO1_IO[9] CAN1_RX
RESERVED
V_SOM
NC
NC
GPIO2_IO[25] CAN2_TX TPM4_CH3 SPI7_PCS1
Ref.
4.6 4.6 4.6 4.6 5.9 5.1 5.9 5.9 5.85. 1 4.9 4.9 4.11 4.14 4.3.2 4.18 4.3.3
4.18 4.10 4.3.3 4.11 4.14 4.18 4.10
5.8
5.1
5.9
5.9
4.18 4.10 4.14 4.11
Revised October 2023
UCM-iMX93 Reference Guide
41
Carrier board Interface
GPIO2_IO[10]
4.18
SPI3_SOUT
4.11
36
NC
5.9
35
TPM4_EXTCLK
4.14
UART7_RTS
4.9
I2C8_SDA
4.12
GPIO2_IO[11]
4.18
SPI3_SCK
4.11
38
NC
5.9
37
TPM5_EXTCLK
4.14
UART7_RTS
4.9
I2C8_SCL
4.12
GPIO2_IO[8]
4.18
SPI3_PCS0
4.11
40
GND
5.1
39
TPM6_CH0
4.14
UART7_TX
4.9
I2C7_SDA
4.12
GPIO2_IO[9]
4.18
SPI3_SIN
4.11
42
NC
5.9
41
TPM3_EXTCLK
4.14
UART7_RX
4.9
I2C7_SCL
4.12
44
NC
5.9
43
V_SOM
5.1
SAI1_RX_DATA[0]
4.3.2
SAI1_MCLK
4.3.2
46
NC
5.9
45
SPI1_SOUT
4.11
UART2_DSR
4.9
MQS1_RIGHT
4.3.3
GPIO1_IO[14]
4.18
48
NC
5.9
47
NC
5.9
GPIO2_IO[27]
4.18
50
NC
5.9
49
CAN2_RX
4.10
TPM6_CH3
4.14
SPI5_PCS1
4.11
SAI1_TX_BCLK
4.3.2
UART2_RTS
4.9
52
NC
5.9
51
SPI1_SIN
4.11
UART1_DSR
4.9
CAN1_RX
4.10
GPIO1_IO[12]
4.18
SAI1_TX_DATA[0]
4.3.2
UART2_RTS
4.9
54
GND
5.1
53
SPI1_SCK
4.11
UART1_DTR
4.9
CAN1_TX
4.10
56
NC
5.9
55
NC
5.9
58
RESERVED
5.8
57
GPIO2_IO[15]
4.18
60
UART3_RX
4.9
59
UART4_RX
4.9
62
NC
5.9
61
64
GND
5.1
63
66
PMIC_STBY_REQ
5.3.1
65
68
PMIC_ON_REQ
5.3.1
67
70
NC
5.9
69
V_SOM
GPIO2_IO[19] SPI5_SIN SPI4_SIN TPM6_CH2
GPIO2_IO[20] SPI5_SOUT SPI4_SOUT TPM3_CH1
GPIO2_IO[21] SPI5_SCK SPI4_SCK TPM4_CH1 JTAG_TMS
GPIO3_IO[29] UART5_RTS JTAG_TDO MQS2_RIGHT CAN2_RX GPIO3_IO[31] UART5_TX
V_SOM
5.1
4.18 4.11 4.11 4.14 4.18 4.11 4.11 4.14 4.18 4.11 4.11 4.14 4.17 4.18 4.9 4.17
4.3.3 4.10 4.18 4.9
5.1
Revised October 2023
UCM-iMX93 Reference Guide
42
Carrier board Interface
UART2_TX
4.9
72
UART1_RTS
4.9
SPI2_SCK
4.11
74
UART1_TX
4.9
SPI2_PCS0
4.11
UART1_RX
4.9
76
SPI2_SIN
4.11
TPM1_CH0
4.14
GPIO1_IO[4]
4.18
78
GND
5.1
80
RESERVED
5.8
82
RESERVED
5.8
84
RESERVED
5.8
86
NC
5.9
88
GND
5.1
90
ALT_BOOT
92 94
96
98
100
Table 60 Pin #
2 4 6 8 10 12 14 16 18
RESERVED
GPIO2_IO[29] I2C3_SCL
GPIO2_IO[16] UART3_RTS SPI4_PCS2 UART4_RTS GPIO2_IO[7] SPI3_PCS1
SPI7_SCK UART6_RTS
I2C7_SCL GPIO2_IO[13] TPM4_CH2 I2C8_SCL
Connector P2
UCM-iMX93 Signal Name
LVDS_TX3_P
LVDS_TX3_N
LVDS_TX2_P
LVDS_TX2_N
GND
LVDS_CLK_P
LVDS_CLK_N
GND
LVDS_TX1_P
5.5
5.8 4.18 4.12 4.18 4.9 4.11 4.9 4.18 4.11 4.11 4.9 4.12 4.18 4.14 4.12
Ref.
4.1.2 4.1.2 4.1.2 4.1.2 5.1 4.1.2 4.1.2 5.1 4.1.2
71
73
75 77 79
81 83 85 87
89 91 93 95
97
99
Pin #
1 3 5 7 9 11 13 15 17
JTAG_TDI MQS2_LEFT
CAN2_TX GPIO3_IO[28] UART5_RX JTAG_TCLK GPIO3_IO[30] UART5_RTS
RESERVED
NC GPIO2_IO[22] SPDIF1_IN TPM5_CH1 TPM6_EXTCLK I2C5_SDA GPIO2_IO[23]
SPDIF1_OUT TPM6_CH1 I2C5_SCL
V_SOM NC
SAI1_TX_SYNC SAI1_TX_DATA[1] SPI1_PCS0 UART2_DTR MQS1_LEFT GPIO2_IO[18]
SPI5_PCS0 SPI4_PCS0 TPM5_CH2 GPIO2_IO[28] I2C3_SDA
VCC_RTC GPIO2_IO[17] UART3_RTS
SPI4_PCS1 UART4_RTS
RESERVED
RESERVED
UCM-iMX93 Signal Name
MIPI_DSI1_D0_N MIPI_DSI1_D0_P MIPI_DSI1_D2_N MIPI_DSI1_D2_P
V_SOM MIPI_DSI1_D3_N MIPI_DSI1_D3_P MIPI_DSI1_D1_N MIPI_DSI1_D1_P
4.17 4.3.3 4.10 4.18 4.9 4.17 4.18 4.9
5.8
4.18 4.3.1 4.14 4.14 4.12 4.18 4.3.1 4.14 4.12 5.1 5.9 4.3.2 4.3.2 4.11 4.9
4.3.3 4.18 4.11 4.11 4.14 4.18 4.12 5.1 4.18 4.9 4.11 4.9
5.8
5.8
Ref.
4.1.1 4.1.1 4.1.1 4.1.1 5.1 4.1.1 4.1.1 4.1.1 4.1.1
Revised October 2023
UCM-iMX93 Reference Guide
43
20 22 24 26 28 30 32 34 36 38 40 42
44
46
48
50
52
54
56
58
60
62 64
Revised October 2023
LVDS_TX1_N
4.1.2
19
GND
5.1
21
LVDS_TX0_P
4.1.2
23
LVDS_TX0_N
4.1.2
25
GND
5.1
27
CSI_CLK_N
4.2
29
CSI_CLK_P
4.2
31
GND
5.1
33
SD3_CLK
4.7
FLEXSPI_SCLK
4.8
35
GPIO3_IO[20]
4.18
SD3_CMD
4.7
FLEXSPI_SS0
4.8
37
GPIO3_IO[21]
4.18
GND
5.1
39
SD3_DATA0
4.7
FLEXSPI_DATA[0]
4.8
41
GPIO3_IO[22]
4.18
SD3_DATA1
4.7
FLEXSPI_DATA[1]
4.8
43
GPIO3_IO[23]
4.18
GND
5.1
45
SD3_DATA2
4.7
FLEXSPI_DATA[2]
4.8
47
GPIO3_IO[24]
4.18
SD3_DATA3
4.7
FLEXSPI _DATA[3]
4.8
49
GPIO3_IO[25]
4.18
GPIO2_IO[6]
4.18
TPM5_CH0
4.14
SPI7_SOUT
4.11
51
UART6_RTS
4.9
I2C7_SDA
4.12
GND
5.1
53
GPIO2_IO[5]
4.18
TPM4_CH0
4.14
SPI7_SIN
4.11
55
UART6_RX
4.9
I2C6_SCL
4.12
GPIO2_IO[4]
4.18
TPM3_CH0
4.14
SPI7_PCS0
4.11
57
UART6_TX
4.9
I2C6_SDA
4.12
ENET1_MDC
4.4.2
UART3_DCB I3C2_SCL
4.9 4.13
59
GPIO4_IO[0]
4.18
ENET1_MDIO
4.4.2
UART3_RIN I3C2_SDA
4.9 4.13
61
GPIO4_IO[1]
4.18
ONOFF
5.3.1
63
UCM-iMX93 Reference Guide
Carrier board Interface
V_SOM MIPI_DSI1_CLK_N MIPI_DSI1_CLK_P
TAMPER0 TAMPER1 V_SOM CSI_D0_N CSI_D0_P
CSI_D1_N
CSI_D1_P
V_SOM ENET2_RD0 UART4_RX SAI2_TX_DATA[2] GPIO4_IO[24] ENET2_RD1 SPDIF1_IN
SAI2_TX_DATA[3] GPIO4_IO[25] ENET2_RD2 UART4_RTS SAI2_MCLK MQS2_RIGHT
GPIO4_IO[26] ENET2_RD3 SPDIF1_OUT SPDIF1_IN MQS2_LEFT GPIO4_IO[27] NC
SD2_RESET GPIO3_IO[7] ENET2_RX_CTL UART4_DSR
SAI2_TX_DATA[0] GPIO4_IO[22] ENET2_RXC SAI2_TX_DATA[1] GPIO4_IO[23]
5.1 4.1.1 4.1.1 4.16 4.16 5.1 4.2 4.2
4.2
4.2
5.1 4.4.2 4.9 4.3.2 4.18 4.4.2 4.3.1 4.3.2 4.18 4.4.2 4.9 4.3.2 4.3.3 4.18
4.4.2 4.3.1 4.3.1 4.3.3 4.18
5.9
4.7 4.18
4.4.2 4.9 4.3.2 4.18
4.4.2 4.3.2 4.18
V_SOM
ENET2_TD0 UART4_TX SAI2_RX_DATA[3] GPIO4_IO[19] ENET2_TD1 UART4_RTS
SAI2_RX_DATA[2] GPIO4_IO[18] ENET2_TD3 SAI2_RX_DATA[0] GPIO4_IO[16]
5.1
4.4.2 4.9 4.3.2 4.18 4.4.2 4.9 4.3.2 4.18 4.4.2 4.3.2 4.18
44
66
POR_B
5.4
ENET2_MDC
4.4.2
68
UART4_DCB SAI2_RX_SYNC
4.9 4.3.2
GPIO4_IO[14]
4.18
ENET2_MDIO
4.4.2
70
UART4_RIN SAI2_RX_BCLK
4.9 4.3.2
GPIO4_IO[15]
4.18
72
GND
5.1
ETH0_MDI0P
4.4.1
74
ENET1_TD3 CAN2_TX
4.4.2 4.10
GPIO4_IO[2]
4.18
GPIO2_IO[14]
4.18
76
UART3_TX
4.9
UART4_TX
4.9
ETH0_MDI1P
4.4.1
78
ENET1_RXC
4.4.2
GPIO4_IO[9]
4.18
ETH0_MDI1N
4.4.1
ENET1_TD1
4.4.2
80
UART3_RTS
4.9
I3C2_PUR
4.13
GPIO4_IO[4]
4.18
82
GND
5.1
ETH0_MDI3P
4.4.1
84
ENET1_RD2
4.4.2
GPIO4_IO[12]
4.18
ETH0_LINK-LED_10_100
4.4.1
86
ENET1_RD0 UART3_RX
4.4.2 4.9
GPIO4_IO[10]
4.18
88
ALT_BOOT_USB
5.5
90
RESERVED
5.8
SD2_CD
4.7
92
ENET1_1588_EVENT0_IN I3C2_SCL
4.4.2 4.13
GPIO3_IO[0]
4.18
SD2_DATA2
4.7
94
ENET2_1588_EVENT1_OUT 4.4.2
GPIO3_IO[5]
4.18
SD2_CLK
4.7
ENET1_1588_EVENT0_OUT 4.4.2
96
I3C2_SDA
4.13
GPIO3_IO[1]
4.18
SD2_DATA3
4.7
98
MQS2_LEFT
4.3.3
GPIO3_IO[6]
4.18
SD2_CMD
4.7
100
ENET2_1588_EVENT0_IN I3C2_PUR
4.4.2 4.13
GPIO3_IO[2]
4.18
Carrier board Interface
ENET2_TD2
4.4.2
65
SAI2_RX_DATA[1]
4.3.2
GPIO4_IO[17]
4.18
ENET2_TX_CTL
4.4.2
67
UART4_DTR SAI2_TX_SYNC
4.9 4.3.2
GPIO4_IO[20]
4.18
ENET2_TXC
4.4.2
69
SAI2_TX_BCLK
4.3.2
GPIO4_IO[21]
4.18
71
V_SOM
5.1
ETH0_MDI0N
4.4.1
73
ENET1_TX_CTL UART3_DTR
4.4.2 4.9
GPIO4_IO[6]
4.18
ETH0_LINK-LED_1000
4.4.1
75
ENET1_TD0 UART3_TX
4.4.2 4.9
GPIO4_IO[5]
4.18
ENET1_TD2
4.4.2
77
CAN2_RX
4.10
GPIO4_IO[3]
4.18
ETH0_MDI2P
4.4.1
79
ENET1_TXC
4.4.2
GPIO4_IO[7]
4.18
ETH0_MDI2N
4.4.1
81
ENET1_RX_CTL UART3_DSR
4.4.2 4.9
GPIO4_IO[8]
4.18
ETH0_LED_ACT
4.4.1
83
ENET1_RD1 UART3_RTS
4.4.2 4.9
GPIO4_IO[11]
4.18
ETH0_MDI3N
4.4.1
85
ENET1_RD3
4.4.2
GPIO4_IO[13]
4.18
87
V_SOM
5.1
89
ADC_IN0
4.15
91
ADC_IN1
4.15
93
ADC_IN2
4.15
95
ADC_IN3
4.15
SD2_DATA0
4.7
97
ENET2_1588_EVENT0_OUT CAN2_TX
4.4.2 4.10
GPIO3_IO[3]
4.18
SD2_DATA1
4.7
99
ENET2_1588_EVENT1_IN CAN2_RX
4.4.2 4.10
GPIO3_IO[4]
4.18
Revised October 2023
UCM-iMX93 Reference Guide
45
6.2 6.3
Carrier board Interface
Mating Connectors
Table 61 Connector type
UCM-iMX93 connector
Ref.
Implementation
P1, P2 Hirose DF40C-100DP-0.4V51
Mfg.
Hirose Hirose
Carrier board (mating) connector P/N P/N
DF40HC(3.0)-100DS-0.4V(51) DF40C-100DS-0.4V51
Mating Height
3.0mm
1.5mm
Mechanical Drawings
· All dimensions are in millimeters. · The height of top side components is <
2.0mm. · Carrier-board connectors provide 1.5 ± 0.15mm board-to-board
clearance. · Board thickness is 1.6mm.
3D model and mechanical drawings in DXF format are available at
https://www.compulab.com/products/computer-on-modules/ucm-imx93-nxp-i-mx9
-somsystem-on-module-computer/#devres
Figure 3 UCM-iMX93 top
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Figure 4 UCM-iMX93 bottom
Carrier board Interface
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7
7.1 7.2 7.3
7.4
Operational Characteristics
OPERATIONAL CHARACTERISTICS
Absolute Maximum Ratings
Table 62 Absolute Maximum ratings
Parameter
Min
Max
Unit
Main power supply voltage (V_SOM) Voltage on any non-power supply pin Backup battery supply voltage (VCC_RTC)
-0.3
6.0
V
-0.5
3.6
V
-0.3
3.8
V
NOTE: Exceeding the absolute maximum ratings may damage the device.
Recommended Operating Conditions
Table 63 Recommended Operating Conditions
Parameter
Min
Typ.
Max
Unit
Main power supply voltage (V_SOM) Backup battery supply voltage (VCC_RTC)
3.45
3.7
5.5
V
1.5
3.0
3.6
V
Typical Power Consumption
Table 64 SOM Typical Power Consumption
Use case
Linux up low-power Linux up typical High CPU load Mixed peripheral load
Use case description
Linux up, Ethernet down, display output off Linux up, Ethernet link up,
display output on LCD CPU stress test (stress-ng) Ethernet activity + flashing
large file to eMMC
ISOM
175mA 300mA 445mA 570mA
Power consumption has been measured with the following setup:
1. Stock module configuration – UCM-IMX93-C1500D-D2-N32-E-WB 2. SB-UCMIMX93 carrier-board, V_SOM = 3.7V 3. 5″ WXGA LCD panel 4. Ambient temperature of 25C
Table 65 OFF Power Consumption
Use case
Use case description
ISOM
OFF mode
Linux shutdown / power-off
1mA
Table 66 RTC timekeeping current
Use case
Use case description
RTC only
VCC_RTC (3.0V) is supplied from external coin-cell battery V_SOM is not present
PSOM 0.64W 1.11W 1.64W 2.11W
PSOM
IVCC_RTC 70nA
ESD Performance
Table 67 ESD Performance
Interface
ESD Performance
i.MX93 pins
2kV Human Body Model (HBM), 500V Charge Device Model (CDM)
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Application Notes
8
APPLICATION NOTES
8.1
Carrier Board Design Guidelines
· Ensure that all V_SOM and GND power pins are connected. · Major power rails
– V_SOM and GND must be implemented by planes, rather than traces.
Using at least two planes is essential to ensure the system signal quality
because the planes provide a current return path for all interface signals.
· It is recommended to put several 10/100uF capacitors between V_SOM and GND
near
the mating connectors.
· Except for a power connection, no other connection is mandatory for UCM-
iMX93
operation. All power-up circuitry and all required pullups/pulldowns are
available onboard UCM-iMX93.
· If for some reason you decide to place an external pullup or pulldown
resistor on a
certain signal (for example – on the GPIOs), first check the documentation of
that signal provided in this manual. Certain signals have on-board
pullup/pulldown resistors required for proper initialization. Overriding their
values by external components will disable board operation.
· You must be familiar with signal interconnection design rules. There are
many sensitive
groups of signals. For example:
· PCIe, Ethernet, USB and more signals must be routed in differential pairs
and by a controlled impedance trace.
· Audio input must be decoupled from possible sources of carrier board noise.
· The following interfaces should meet the differential impedance requirements
with
manufacturer tolerance of 10%:
· USB2.0: DP/DM signals require 90 ohm differential impedance.
· All single-ended signals require 50 ohm impedance.
· PCIe TX/RX data pairs and PCIe clocks require 85 ohm differential impedance.
· Ethernet, MIPI-CSI and MIPI-DSI signals require 100 ohm differential
impedance.
· Bear in mind that there are components on the bottom side of UCM-iMX93. It
is not
recommended to place any components underneath the UCM-iMX93 module.
· Refer to the SB-UCMIMX93 carrier board reference design schematics. · It is
recommended to send the schematics of the custom carrier board to Compulab
support team for review.
8.2
Carrier Board Troubleshooting
· Using grease solvent and a soft brush, clean the contacts of the mating
connectors of
both the module and the carrier board. Remnants of soldering paste can prevent
proper contact. Take care to let the connectors and the module dry entirely
before re-applying power otherwise, corrosion may occur.
· Using an oscilloscope, check the voltage levels and quality of the V_SOM
power supply. It
should be as specified in section 7.2. Check that there is no excessive ripple
or glitches. First, perform the measurements without plugging in the module.
Then plug in the module and measure again. Measurement should be performed on
the pins of the mating connector.
· Using an oscilloscope, verify that the GND pins of the mating connector are
indeed at
zero voltage level and that there is no ground bouncing. The module must be
plugged in during the test.
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Application Notes
· Create a “minimum system” – only power, mating connectors, the module and a
serial
interface.
· Check if the system starts properly. In system larger than the minimum,
possible sources
of disturbance could be:
· Devices improperly driving the local bus · External pullup/pulldown
resistors overriding the module on-board values, or any other
component creating the same “overriding” effect
· Faulty power supply · In order to avoid possible sources of disturbance, it
is strongly recommended to start
with a minimal system and then to add/activate off-board devices one by one.
· Check for the existence of soldering shorts between pins of mating
connectors. Even if
the signals are not used on the carrier board, shorting them on the connectors
can disable the module operation. An initial check can be performed using a
microscope. However, if microscope inspection finds nothing, it is advisable
to check using an X-ray, because often solder bridges are deep beneath the
connector body. Note that solder shorts are the most probable factor to
prevent a module from booting.
· Check possible signal short circuits due to errors in carrier board PCB
design or assembly. · Improper functioning of a customer carrier board can
accidentally delete boot-up code
from UCM-iMX93, or even damage the module hardware permanently. Before every
new attempt of activation, check that your module is still functional with
CompuLab SBUCMIMX93 carrier board.
· It is recommended to assemble more than one carrier board for prototyping,
in order to
ease resolution of problems related to specific board assembly.
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References
- Compulab
- Compulab
- ARM System on Modules | Computer on Modules | Compulab
- UCM-iMX93 | NXP i.MX9 SOM | System-on-Module | Computer-on-Module | CompuLab
- UCM-iMX93 | NXP i.MX9 SOM | System-on-Module | Computer-on-Module | CompuLab
- UCM-iMX93 | NXP iMX9 SOM | System-on-Module | Computer-on-Module | CompuLab