Microsemi SmartFusion2 MSS MMUART Configuration User Guide
- June 10, 2024
- Microsemi
Table of Contents
SmartFusion2 MSS MMUART Configuration
User Guide
Introduction
The SmartFusion2 Micro controller Subsystem (MSS) provides two MMUART hard
peripherals (APB_0 and APB_1 sub busses) with Full/Half Duplex, Asynchronouss/
Synchronous mode and Modem interface option.
On the MSS Canvas, you must enable (default) or disable each MMUART instance
based on whether it is being used in your current application. Disabled MMUART
instances are held in reset (lowest power state). By default, ports of enabled
MMUART instances are configured to connect to the device Multi Standard I/Os
(MSIOs). Note that MSIOs allocated to a MMUART instance are shared with other
MSS peripherals. These shared I/Os are available to connect to MSS GPIOs and
other peripherals when the MMUART instance is disabled or if the MMUART
instance ports are connected to the FPGA fabric.
The functional behavior of each MMUART instance must be defined at the
application level using the SmartFusion2 MSS MMUART Driver provided by
Microsemi.
In this document, we describe how you to configure the MSS MMUART instances
and define how the peripheral signals are connected.
For more details about the MSS MMUART hard peripherals, please refer to the
SmartFusion2 User Guide.
Configuration Options
Duplex Mode:
- Full Duplex – Provides two signals for serial data, RXD and TXD
- Half Duplex – Provides a single signal for serial data, TXD_RXD
Async/Sync Mode – Selecting Synchronous mode provides a CLK signal.
Modem Interface – Selecting the Modem interface enables access to
individual ports in the MODEM port group.
Peripheral Signals Assignment Table
The SmartFusion2 architecture provides a very flexible schema for connecting
peripheral signals to either MSIOs or the FPGA fabric. Use the signal
assignment configuration table to define what your peripheral is connected to
in your application. The assignment table has the following columns (Figure
2-1):
MSIO – Identifies the peripheral signal name configured in a given row.
Main Connection – Use the drop-down list to select whether the signal is
connected to an MSIO or the FPGA fabric.
Direction – Indicates if the signal direction is IN, OUT or IN OUT.
Package Pin – Shows the package pin associated with the MSIO when the
signal is connected to an MSIO.
Extra Connections – Use the Advanced Options check-box to view the extra
connection options:
- Select the Fabric option to observe into the FPGA fabric a signal that is connected to an MSIO.
- Select the GPIO option to observe an input direction signal – from either the FPGA fabric or an MSIO – using an MSS GPIO.
Connectivity Preview
The Connectivity Preview panel on the right of the MSS MMUART Configurator dialog shows a graphical view of the current connections for the highlighted signal row (Figure 3-1).
Resource Conflicts
Because MSS peripherals (MMUART, I2C, SPI, CAN, GPIO, USB, Ethernet MAC) share
MSIO and FPGA fabric access resources, the configuration of any of these
peripherals may result in a resource conflict when you configure an instance
of the current peripheral. Peripheral configurations provide clear indicators
when such a conflict arises.
Resources used by a previously configured peripheral result in three types of
feedback in the current peripheral configurator:
- Information – If a resource used by another peripheral does not conflict with the current configuration, an information icon appears in the connectivity preview panel, on that resource. A tool tip on the icon provides details about which peripheral uses that resource.
- Warning/Error – If a resource used by another peripheral conflicts with the current configuration, a warning or error icon appears in the connectivity preview panel, on that resource. A tool tip on the icon provides details about which peripheral uses that resource.
When errors are displayed you will not be able to commit the current
configuration. You can either resolve the conflict by using a different
configuration or cancel the current configuration using the Cancel button.
When warnings are displayed (and there are no errors), you can commit the
current configuration. However, you cannot generate the overall MSS; you will
see generation errors in the Libero SoC log window. You must resolve the
conflict that you created when you committed the configuration by re
configuring either of the peripherals causing the conflict.
The peripheral configurations implement the following rules to determine if a
conflict should be reported as an error or a warning.
- If the peripheral being configured is the GPIO peripheral then all conflicts are errors.
- If the peripheral being configured is not the GPIO peripheral then all conflicts are errors unless the conflict is with a GPIO resource in which case conflicts will be treated as warnings.
Error Example
The USB peripheral is used and uses the device PAD bounded to package pin H27.
Configuring the MMUART_0 peripheral such that the TXD_RXD port is connected to
an MSIO will result in an error.
Figure 4-1 shows the error icon displayed in the connectivity assignment
table for the TXD_RXD port.
Figure 4-2 shows the error icon displayed in the preview panel on the PAD resource for the TXD_RXD port.
Warning Example
The GPIO peripheral is used and uses the device PAD bounded to package pin H27
(GPIO_27).
Configuring the MMUART_0 peripheral such that the TXD_RXD port is connected to
an MSIO will result in a warning.
Figure 4-3 shows the warning icon displayed in the connectivity
assignment table for the TXD_RXD port.
Figure 4-4 shows the warning icon displayed in the preview panel on the PAD resource for the TXD_RXD port.
Information Example
The USB peripheral is used and uses the device PAD bounded to package pin H27
(Figure 4-5).
Configuring the MMUART_0 peripheral such that the TXD_RXD port is connected to
the FPGA fabric does not result in a conflict. However, to indicate that he
PAD associated with the TXD_RXD port (but not used in this case), the
information icon is displayed in the preview panel. A tool tip associated with
the icon provides a description of how the resource is used (USB in this
case).
Port Description
Table 5-1 • Port Description
| Port Name | Port Group | Direction | Description |
|---|---|---|---|
| TXD | MMUART_ |
||
| MMUART_ |
Out | Serial output data in Full Duplex mode. This is the |
data that will be transmitted from Core16550. It is synchronized with the BAUD
OUT output pin.
RXD| MMUART_
MMUART
TXDRXD| MMUART
MMUART
CLK| MMUART
MMUART
RTS| MMUART
This active high output signal is used to inform the attached device (modem)
that Core16550 is ready to send data. It is programmed by the CPU via the
Modem Control Register.
DTR| MMUART
This active high output signal informs the attached device (modem) that
Core16550 is ready to establish a communications link. It is programmed by the
CPU via the Modem Control Register.
DSR| MMUART
This active high signal is an input indicating when the attached device
(modem) is ready to set up a link with Core16550. Core16550 passes this
information to the CPU via the Modem Status Register. This register also
indicates if the DSR signal has changed since the last time the register was
read.
CTS| MMUART
This active high signal is an input showing when the attached device (modem)
is ready to accept data. Core16550 passes this information to the CPU via the
Modem Status register. This register also indicates if the CTS signal has
changed since the last time the register was read.
Port Name| Port Group| Direction| Description
---|---|---|---
RI| MMUART
\MMUART
This active high signal is an input showing when the attached device (modem)
has sensed a ring signal on the telephone line. Core16550 passes this
information to the CPU via the Modem Status Register. This register also
indicates when the RI trailing edge was sensed.
DCD| MMUART
This active high signal is an input indicating when the attached device
(modem) has detected a carrier.
Core16550 passes this information to the CPU via the Modem Status Register.
This register also indicates if the DCD signal has changed since the last time
the register was read.
Note
- Port names have the name of the MMUART instance as a prefix, e.g. MMUART_
_TXD_RXD. - Fabric ‘main connection’ input ports names have “F2M” as a suffix, e.g. MMUART _
_RXD_F2M. - Fabric ‘extra connection’ input ports names have “I2F” as a suffix, e.g. MMUART_
_TXD_RXD_I2F. - Fabric output and output-enable ports names have “M2F” and “M2FOE” as a suffix, e.g. MMUART
_TXD_RXDM2F and MMUART _ TXD_RXD_M2F_OE. - PAD ports are automatically promoted to top throughout the design hierarchy.
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References
- Microsemi | Semiconductor & System Solutions | Power Matters
- Libero® SoC Design Suite Versions 2023.2 to 12.0 | Microchip Technology
- Libero® SoC Design Suite Versions 2023.2 to 12.0 | Microchip Technology
- Libero® SoC Design Suite Versions 2023.2 to 12.0 | Microchip Technology
- Libero® SoC Design Suite Versions 2023.2 to 12.0 | Microchip Technology
- Libero® SoC Design Suite Versions 2023.2 to 12.0 | Microchip Technology
- Libero® SoC Design Suite Versions 2023.2 to 12.0 | Microchip Technology
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