SEGGER J-Link-OB-RA4M2 On Board Debug Probe

Disclaimer
The information written in this document is assumed to be accurate without guarantee. The information in this manual is subject to change for functional or performance improvements without notice. SEGGER Microcontroller GmbH (SEGGER) assumes no responsibility for any errors or omissions in this document. SEGGER disclaims any warranties or conditions, express, implied or statutory for the fitness of the product for a particular purpose. It is your sole responsibility to evaluate the fitness of the product for any specific use.

Copyright notice
You may not extract portions of this manual or modify the PDF file in any way without the prior written permission of SEGGER. The software described in this document is furnished under a license and may only be used or copied in accordance with the terms of such a license. © 2022-2022 SEGGER Microcontroller GmbH, Monheim am Rhein / Germany

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Manual versions
This manual describes the current software version. If you find an error in the manual or a problem in the software, please report it to us and we will try to assist you as soon as possible. Contact us for further information on topics or functions that are not yet documented.
Print date: July 18, 2022

About this document

Assumptions
This document assumes that you already have a solid knowledge of the following:

• The software tools used for building your application (assembler, linker, C compiler).
• The C programming language.
• The target processor.
• DOS command line.

If you feel that your knowledge of C is not sufficient, we recommend The C Programming Language by Kernighan and Richie (ISBN 0–13–1103628), which describes the standard in C programming and, in newer editions, also covers the ANSI C standard.

How to use this manual
This manual explains all the functions and macros that the product offers. It assumes you have a working knowledge of the C language. Knowledge of assembly programming is not required.

Typographic conventions for syntax
This manual uses the following typographic conventions:

display (that is system functions, file- or pathnames).
Parameter| Parameters in API functions.
Sample| Sample code in program examples.
Sample comment| Comments in program examples.
Reference| Reference to chapters, sections, tables and figures or other documents.
GUI Element| Buttons, dialog boxes, menu names, menu commands.
Emphasis| Very important sections.

Chapter 1 Why J-Link OB?

The J-Link on-board (J-Link OB) was designed in order to provide a low-cost, space-saving and on-board alternative to the general J-Link, for eval board manufacturers. J-Link OB can be used with the same software package as the general J-Links and can be used with the same utilities (as far as the feature set of the J-Link OB supports this)
Note It is not allowed to use J-Link-OB-RA4M2 for stand-alone emulators.

Chapter 2 Supported target CPU cores

For a list of cores supported by this J-Link OB model, please refer to here: J-Link OB Model overview

Chapter 3 Supported target interfaces

The J-Link-OB-RA4M2 supports the following target interfaces:

• JTAG
• cJTAG
• SWD
• SWO
• 1x virtual COM port (VCOM) + optional hardware flow control

Target interface pins

The J-Link-OB-RA4M2 provides the following target interface signals:

• TCK/SWCLK (P102)
• TMS/SWDIO (P101)
• TDI (P103)
• TDO/SWO (P100)

• RESET (P112)

• TXD_VCOM (P302)
• RXD_VCOM (P301)
• CTS_VCOM (P409)
• RTS_VCOM (P408)

Which signals are required depends on what features shall be supported on the evaluation board. If support for a specific feature or interface is not required, the spare pins should be left open. For more information about which target interface requires which signals, please refer to the following sections.

Target interface JTAG

If JTAG support is required on the target hardware to be designed, the following signals need to be connected:

• TCK (P102)
• TMS (P101)
• TDI (P103)
• TDO (P100)

• RESET (P112)

Note
TCK and TMS share functionality with the SWCLK and SWDIO pins used for the SWD interface. So if JTAG connected on the J-Link OB, SWD is supported automatically as well.

Target interface SWD

If SWD (+ optional SWO) support is required on the target hardware to be designed, the following signals need to be connected:

• SWCLK (P102)
• SWDIO (P101)
• SWO (P100)

• RESET (P112)

If SWO support is not required (e.g. when the target CPU is Cortex-M0/M0+ based, which does not provide SWO support), the SWO signal can be left open.

Target interface VCOM

This J-Link OB model can support up to 1x virtual COM port (VCOM) as an optional and additional target interface. For more information about what VCOM is, please refer to JLink VCOM functionality . If VCOM (+ optional hardware flow control) support is required on the target hardware to be designed, the following signals need to be connected:

• TXD (P302)
• RXD (P301)
• CTS (P409)
• RTS (P408)

If hardware flow control support is not required, the CTS and RTS signal can be left open.

Note
VCOM is an optional feature that needs to be ordered explicitly when ordering J-Link OB licenses.

Chapter 4

Compatible MCUs as J-Link OB host

The J-Link-OB-RA4M2 is based on the Renesas RA4M2 100 MHz, 128 KB flash, 24 KB RAM series MCUs. The following microcontrollers are compatible to this J-Link OB model: · R7FA4M2AB3CNE (512 KB flash, 48-pin QFN) Untested but pin, flash and RAM compatible:

• R7FA4M2AB3CFL (512 KB flash, 48-pin LQFP)
• R7FA4M2AB3CFM (512 KB flash, 64-pin LQFP)
• R7FA4M2AB3CFP (512 KB flash, 100-pin LQFP)
• R7FA4M2AC3CFP (384 KB flash, 100-pin LQFP)
• R7FA4M2AC3CFM (384 KB flash, 64-pin LQFP)
• R7FA4M2AC3CFL (384 KB flash, 48-pin LQFP)
• R7FA4M2AC3CNE (384 KB flash, 48-pin QFN)
• R7FA4M2AB3CFP (256 KB flash, 100-pin LQFP) The untested devices may be used as alternative to the tested ones but are excluded from support.

Chapter 5 Schematics

CHAPTER 6 Glossary

This chapter describes important terms used throughout this manual.

Adaptive clocking
A technique in which J-Link / J-Trace sends out a clock signal and waits for the returned clock from the target device before generating the next clock pulse. The technique allows the J-Link / J-Trace interface unit to adapt to different signal drive capabilities, different cable lengths and variable target clock speeds. Adaptive clocking can be used when it is supported by the connected target device.

RESET
Abbreviation of System Reset. The electronic signal which causes the target system other than the TAP controller to be reset. This signal is also known as “nSRST” “nSYSRST”, “nRST”, or “nRESET” in some other manuals. See also nTRST.

nTRST
Abbreviation of TAP Reset. The electronic signal that causes the target system TAP controller to be reset. This signal is known as nICERST in some other manuals. See also nSRST.

RTCK
Returned TCK. The signal which allows Adaptive Clocking.

TCK
The electronic clock signal which times data on the TAP data lines TMS, TDI, and TDO.

TDI
The electronic signal input to a TAP controller from the data source (upstream). Usually, the TDI signal of J-Link is connected to the TDI of the first TAP controller in a JTAG chain.

TDO
The electronic signal output from a TAP controller to the data sink (downstream). Usually, the TDO signal of J-Link is connected to the TDO of the last TAP controller in a JTAG chain.

TMS
The electronic signal Test Mode Select is an input to the TAP controller and it is used to select different stages of state machine. It is clocked in into the TAP controller using the TCK signal.(upstream). Usually, the TMS output signal of J-Link is connected to the TMS input of the first TAP controller in a JTAG chain. For Cortex-M CPUs this signal may also be used as the bidirectional data signal SWDIO when the CPU is accessed in serial wire debug mode SWD.

SWD
A serial communication protocol for Cortex M CPUs which may used for communication with a debug device as an alternative communication channel to JTAG. The SWD communication uses less pins.

SWDIO
The bidirectional electronic signal for communication of a Cortex M CPU accessed in serial wire debug mode. Normally, the TMS input pin of the Cortex M CPU is used as SWDIO pin in serial wire mode.

SWCLK
The electronic signal which times data on the SWDIO data line used in serial wire debug mode. The SWCLK pin is typically the TCK pin used as JTAG clock input, when JTAG is also supported by the device.

SWO
The electronic asynchronous signal for trace data output or SWV output data which may be sent by the application on a Cortex-M CPU running in serial wire debug mode. J-Link-OBRA4M2 is able to receive the data in asynchronous mode when SWO of the target CPU is connected to the SWOin signal of J-Link-OB- RA4M2. Normally the SWO output signal of a Cortex-M CPU is directed via the TDO signal pin, but may be separated on some devices.

References

• Software Development Tools by SEGGER – The Embedded Experts

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