EVAL-LT3078-AZ Evaluation Board Analog Devices User Guide
- June 1, 2024
- Analog Devices
Table of Contents
EVAL-LT3078-AZ Evaluation Board Analog Devices
Product Information
Specifications
- Input voltage range: 0.6 V to 5.5 V
- BIAS voltage range: 2.375 V to 5.5 V
- Programmable output voltage range: 0.5 V to 4.2 V
- Maximum output current: 5 A
- BNC connectors for noise and PSRR measurement
- Regulator can be turned on or off using a jumper
- Terminals for output current, temperature, and output regulation status monitoring
- VIOC pin manages power dissipation and PSRR
- Banana jacks for minimizing voltage drops in connections
Product Usage Instructions:
Power Connection
Connect the DC power supply within the input voltage range to the
appropriate terminals on the evaluation board.
Output Voltage Programming:
Use jumpers according to the selection matrix to set the desired output
voltage within the programmable range.
Current Limit Selection:
Choose between 2.5 A or 5.5 A output current limits using jumper and
resistor combinations. The IMON pin can be shorted to ground to disable
external current-limit programming.
Monitoring
Utilize the provided terminals for monitoring output current, temperature,
and regulation status.
Thermal Management:
Ensure proper board layout for optimal thermal performance of the
regulator.
FAQ
-
Q: What should I do if the output voltage is not within the programmed range?
A: Check the jumper settings and ensure proper connections to the input voltage source. -
Q: How can I disable current-limit programming?
A: Short the IMON pin to ground using the CURRENT LIMIT jumper.
Evaluating the LT3078 5A, Ultra-Low Noise, High PSRR, 55 mV Dropout Ultra- Fast Linear Regulator
FEATURES
- Input voltage range: 0.6 V to 5.5 V
- BIAS voltage range: 2.375 V to 5.5 V
- Jumpers program output voltage according to selection matrix: 0.5 V to 4.2 V
- Maximum output current: 5 A
- BNC connectors for noise and PSRR measurement
- Jumper and resistor combinations select either 5.5 A or 2.5 A output current limit and commensurate monitoring or disable programmed current limit and monitoring
- Jumper turns regulator on or off
- Terminals provide output current, temperature, and output regu-lation status monitoring
- Jumper to margin output voltage ±2.5%
- The VIOC pin of the LT3078 manages power dissipation and PSRR
- Banana jacks minimize VIN and VOUT connection voltage drops
- VO+, VO−, and VI+ terminals for regulation and dropout monitor-ing
- Configurable load-transient circuit for load response testing
- Thermally enhanced, 22-lead, 3 mm × 4 mm x 0.95 mm, LQFN package
EVALUATION KIT CONTENTS
EVAL-LT3078-AZ evaluation board
EQUIPMENT NEEDED
- DC power supplies
- Multimeters for voltage and current measurements
- Electronic or resistive load
DOCUMENTS NEEDED
LT3078 data sheet
EVALUATION BOARD PHOTOGRAPH
REVISION HISTORY
10/2023—Revision 0: Initial Version
GENERAL DESCRIPTION
-
The EVAL-LT3078-AZ evaluation board features the LT3078, a 5 A, ultra-low noise, high power-supply rejection ratio (PSRR), 55 mV dropout ultra-fast linear regulator. The input voltage (VIN) range for the VIN power is from 0.6 V to 5.5 V. There are jumpers to
set a 3-bit trilevel code that determines the output voltage (VOUT) at preprogrammed levels that range from 0.5 V to 4.2 V. The maximum output current is 5 A. The EVAL-LT3078-AZ requires an external BIAS voltage (VBIAS) that is at least 1.2 V higher than VOUT and is between 2.375 V and 5.5 V. -
The LT3078 of the EVAL-LT3078-AZ requires few external com-ponents, therefore, simplifying circuit design. External component choice with careful printed circuit board (PCB) design helps to optimize noise, PSRR, load-transient response, and VOUT regula-tion performance. The LT3078 requires capacitors for the internal reference, power input, BIASF pin, and the power output. The internal reference is bypassed with a 16 V, 0805 sized, 4.7 µF capacitor to reduce output noise and program the soft-start. Larger capacitor case sizes and higher voltage ratings decrease 1/f noise for otherwise comparable capacitors. The 10 µF x2 capacitor at the circuit output was chosen for high-frequency PSRR performance and to optimize VOUT response during load transients.
-
The capacitor that bypasses the VIN power for the LT3078 and the corresponding VIN PCB layout can affect PSRR (for additional information, see the Best PSRR Performance: PCB
-
Layout for Input Traces section). The EVAL-LT3078-AZ decouples the VIN power with a 47 µF capacitor. Less VIN capacitance can improve PSRR at high frequencies (for the minimum capacitor value required for VIN, see the LT3078 data sheet). Note that a bulk 220 µF tanta-lum polymer capacitor further reduces VIN variation during load transients and reduces input voltage ringing that can be caused by inductive input power leads. The PCB has a footprint for an optional Subminiature Version A (SMA) connector that allows a shielded VIN power connection to the PCB edge, if required.
-
The EVAL-LT3078-AZ bypasses the BIASF pin with a 2.2 µF ca-pacitor instead of the VBIAS supply input. Because the BIASF pin is isolated from VBIAS by a resistance that is internal to the LT3078, there is less PSRR degradation when BIASF is bypassed compared to when VBIAS is bypassed. Otherwise, the effect on PSRR of the VIN and VBIAS bypass capacitors is similar.
-
The EVAL-LT3078-AZ has resistors that allow a CURRENT LIMIT jumper to select output current limits of either 2.5 A or 5.5 A. The CURRENT LIMIT jumper can also disable external current-limit pro-gramming by shorting the IMON pin to ground. An IMON terminal is available for current monitoring. The IMON voltage is the product of the resistance that externally programs current limit and the IMON pin current that is 1/5000 of the output current. Externally programmed current limit occurs when the IMON voltage is 1 V.
-
A POWER jumper (JP1) is available on the EVAL-LT3078-AZ to either connect the EN pin to VBIAS to turn the output on or to ground to disable the output. A TEMP terminal is also available for die temperature monitoring. There is a PG terminal that is pulled up to VBIAS by a 51 kΩ resistor and pulled down by the open-drain, negative channel metal-oxide semiconductor (NMOS) PG pin output for indication of regulator output status and other fault modes. The voltage input-to-output control (VIOC) terminal allows connections for automatically controlling a preregulation voltage. In addition, a MARG jumper can margin the output voltage to either ±2.5%.
-
Banana jacks minimize voltage drops on VIN and VOUT connec-tions. Bayonet Neill-Concelman (BNC) connectors provide low noise connections to power VIN, VBIAS, and VOUT. The EVAL-LT3078-AZ PCB design uses a split-capacitor technique to Kelvin connect the ground terminal of the REF capacitor to the ground terminal of the output capacitor, and the SENSE pin to the positive terminal of the output capacitor. The VO+, VO−, and VI+ terminals Kelvin connect to VIN and VOUT and are the optimum place to ob-serve output voltage regulation and dropout voltage performance. There are test points for BIASF and REF voltages.
-
The EVAL-LT3078-AZ includes a load-transient circuit for load re-sponse testing. A 2512 size power resistor must be installed with a resistance that achieves the required transient current, but all the remaining circuit components are provided including a 10 kΩ gate pull-down resistor, a 4.7 nF Miller capacitor and a high-current NMOS. Additionally, a banana jack makes it possible to return an external DC load through the same 0.02 Ω sense resistor that is the return for the transient current so both can be monitored together.
-
The EVAL-LT3078-AZ has placeholders identified on the schematic as optional DNI components that make it convenient to add capaci-tance (for more information, see Figure 8).
-
Full specifications on the LT3078 are available in the LT3078 data sheet available from Analog Devices, Inc., and must be consulted with this user guide when using the EVAL-LT3078-
-
AZ evaluation board. The LT3078 of the EVAL-LT3078-AZ features a thermally enhanced, 22-lead, 3 mm x 4 mm x 0.95 mm LQFN package. Proper board layout is essential for maximum thermal performance.
-
Design files are available on the EVAL-LT3078-AZ evaluation board website page.
PERFORMANCE SUMMARY
Specifications are at TA = 25°C, unless otherwise noted.
Table 1. Performance Summary
Parameter Symbol Test Conditions/Comments
Min Typ Max Unit
INPUT VOLTAGE
Minimum Maximum
| VIN| **** IOUT = 300 mA
VOUT = 1.5 V, IOUT = 5 A
| **** 5.5
1.91
| | 0.6| V V V
---|---|---|---|---|---|---
BIAS VOLTAGE
Minimum Maximum
| VBIAS| VBIAS ≥ VOUT + 1.2 V| **** 5.5| | 2.375| V V
OUTPUT VOLTAGE| VOUT| VOUT = 0.5 V, 50 mA ≤ IOUT ≤ 5 A, VIN = 0.8 V| 0.492|
0.500| 0.508| V
| | VOUT = 1.2 V, 10 mA ≤ IOUT ≤ 5 A, VIN = 1.5 V| 1.182| 1.200| 1.218| V
| | VOUT = 3.3 V, 10 mA ≤ IOUT ≤ 5 A, VIN = 3.6 V| 3.250| 3.300| 3.35| V
| | VOUT = 4.2 V, 10 mA ≤ IOUT ≤ 5 A, VIN = 4.5 V| 4.137| 4.200| 4.263| V
OUTPUT CURRENT| IOUT| | | | |
Maximum| | | 5| | | A
Minimum| | VOUT < 0.8 V| | | 50| mA
| | VOUT ≥ 0.8 V| | | 10| mA
Limit| | IMON resistor (RIMON) = 2 kΩ (2.5 A jumper position)| 2.35| 2.5|
2.65| A
| | RIMON = 909 Ω (5.5 A jumper position)| 5.33| 5.5| 5.67| A
BIAS PIN NAP MODE CURRENT| IBIAS| VBIAS = 5.5 V, EN = 0 V, R1 = open| 10| µA
IN PIN NAP MODE CURRENT| IIN| VIN = 5.5 V, EN = 0 V| 500| µA
1 The maximum power dissipation and, consequently, the maximum input voltage for an output that is programmed to 1.5 V with a 5 A load is set by the 60°C temperature rise of the LT3078 on the evaluation board. Higher input voltages can be reached if larger copper area or forced-air cooling is applied. In addition, consider the effect of ambient temperature and the maximum junction temperature that may occur. For more information, see the LT3078 data sheet.
QUICK START PROCEDURE
To use the EVAL-LT3078-AZ to evaluate the performance of the LT3078, and for
the proper measurement equipment setup, see Figure 2 and do the following
steps:
-
With the input supplies off and turned down and the load turned down, make all the connections shown in Figure 2. Ensure that the VO2, VO1, and VO0 jumpers to set VOUT are in the proper positions for the required VOUT according to the VOUT selection matrix table in the LT3078 data sheet. In addition, ensure that the POWER jumper (JP1) is in the ON position, the CURRENT LIMIT jumper (JP5) is in the 5.5A position, and the MARG jumper (JP6) is in the OPEN position.
-
Turn on the input and bias supplies and increase the input supply so it is at least 200 mV above the programmed output voltage. Adjust VBIAS so it is between 2.375 V and 5.5 V and at least 1.2 V higher than the programmed VOUT for proper operation. Note that when setting the input and bias voltages, a VIN or VBIAS that is too close to the programmed VOUT
(too low) can cause dropout operation and a loss of VOUT regulation. Also, a VIN that is too high above the output can increase power dissipation to an unacceptable level. -
Increase the load to the required IOUT. Readjust the input sup-ply so it is still at least 200 mV above the programmed output voltage. Verify that VOUT is the expected voltage programmed by the jumpers. Note that if VOUT is lower than expected, the load may be set too high. Temporarily disconnect the load to ensure that it is not set too high.
-
When the proper VOUT is established, adjust the input voltages and load within the operating ranges and observe the VOUT regulation and other parameters. For load response testing details, see the next section.
-
For measuring output noise and PSRR, refer to the Application Note AN-83, Performance Verification of Low Noise, Low Dropout Regulators and Application Note AN-159, Measuring 2 nV/√Hz Noise and 120 dB Supply Rejection on Linear Regula-tors. Note that J3, J4, and J5 are BNC connectors that are used for noise and PSRR measurements.
-
Note that the CURRENT LIMIT jumper can additionally select a 2.5 A current limit or the INTERNAL current limit that the LT3078 provides. Monitor the output current at the IMON terminal when the 2.5 A or 5.5 A current limits are selected.
-
Use the MARG jumper to margin the output voltage higher or lower.
-
Monitor power good and temperature at the PG and TEMP terminals, respectively.
-
For the usage of the VIOC terminal, refer to the LT3078 data sheet .
The EVAL-LT3078-AZ includes a load-transient circuit for load response testing. Take the following steps to perform load response testing using the load-transient circuit.
- Install 2512 size power resistor R4 with a resistance that achieves the required transient current. Do not exceed the surge current rating of the resistor. Keep the resistor within its power dissipation limits by limiting the time duration that it conducts.
- For the proper load response testing equipment setup, see Figure 3. Return the external DC load current to the 0.02 Ω sense resistor R5 via the Q1_S banana jack so the transient current and DC load current can both be monitored together using the Q1_S and GND test points.
- Drive the gate of the high-current NMOS Q1 using the Q1_G and GND test points. Usually a pulse generator with a 0 V
to 5 V level output is adequate to drive the NMOS gate. The pulse generator output voltage levels, its transition times and the value of the Miller capacitor C16 all affect the load-transient current rise and fall times.
PRINTED CIRCUIT BOARD (PCB) LAYOUT
BEST PSRR PERFORMANCE: PCB LAYOUT FOR INPUT TRACES
For applications using the LT3078 for post-regulating switching converters,
placing a capacitor directly at the LT3078 input results in AC current (at the
switching frequency) to flow near the LT3078. Without careful attention to the
PCB layout, this relatively high-fre-quency switching current generates an
electromagnetic field (EMF) that couples to the LT3078 output, degrading its
effective PSRR. While highly dependent on the PCB, the switching preregulator,
the input capacitor size, among other factors, the PSRR can easily degrade at
high frequencies. This degradation is present even if the LT3078 is desoldered
from the board because it effectively degrades the PSRR of the PCB itself.
While negligible for conven-tional low PSRR low dropout (LDO) regulators, the
high PSRR of the LT3078 requires careful attention to higher-order parasitics
to realize the full performance offered by the regulator.
The EVAL-LT3078-AZ alleviates this degradation in PSRR by using a specialized
layout technique. On Layer 3, the input trace (VIN) is highlighted in red (for
more information, see Figure 4), with the return path (GND) highlighted on
Layer 4 together with the CIN1 input capacitor (for more information, see
Figure 5). When an AC voltage is applied to the input of the EVAL-LT3078-AZ,
AC current flows on the path formed through CIN1 by the input and ground
traces. Without the proper PCB layout, the AC current that flows on this path
can generate EMFs that do not completely cancel and couple to the C3 output
capacitor and related traces, which makes the PSRR appear worse than it
actually is. With the input trace directly above the return path, the EMFs are
in opposite directions, and consequently, cancel each other out. Ensure that
these traces exactly overlap each other to maximize the cancellation effect
and thus provide the maximum PSRR offered by the regulator.
PCB LAYOUT FOR THE C3 OUTPUT CAPACITOR
As mentioned in the General Description section, the EVAL-LT3078-AZ PCB design
uses a split-capacitor technique to Kelvin connect the ground terminal of the
REF capacitor to the ground terminal of the C3 output capacitor and the SENSE
pin to the positive terminal of the output capacitor (for more information,
see Figure 6 and Figure 7). This Kelvin connection regulates the output
voltage at the output capacitor, which in turn, optimizes noise, PSRR, load
transient, and regulation performance that is all measured at the output
capacitor. The split-capacitor technique is useful in this case because it
makes it possible to relocate the regulation point, if required. Regulation of
the output voltage at
a new location requires leaving the C3 output-capacitor location open and
wiring the split-capacitor pads corresponding to the REF capacitor ground
terminal and SENSE to the new output capacitor location. Additional
capacitance located from SENSE to the REF ground between the regulation point
and the LT3078 decreases sta-bility. The split-capacitor technique itself does
not enhance LT3078 stability because of the type of pass transistor, even
though the unity-gain bandwidth of the LT3078 bandwidth is relatively high and
close to the self-resonance frequency of the output capacitor.
PRINTED CIRCUIT BOARD (PCB) LAYOUT
EVALUATION BOARD SCHEMATIC
Figure 8. EVAL-LT3078-AZ Evaluation Board Schematic
ORDERING INFORMATION
BILL OF MATERIALS
Table 2. Bill of Materials for EVAL-LT3078-AZ
Item Quantity1 Reference Designator Part Description
Required Circuit Components| | | |
---|---|---|---|---
1| 1| C1| 4.7 μF capacitor, X7R, 16 V, 10%, 0805, soft termination| Murata,
GCJ21BR71C475KA01L
2| 1| C2| 2.2 μF capacitor, X7R, 10 V, 10%, 0603| Murata, GRM188R71A225KE15D
3| 2| C3, C4| 10 μF capacitors, X7S, 25 V, 10%, 1206| Murata,
GCM31CC71E106KA03L
4| 1| CIN1| 47 μF capacitor, X5R, 10 V, 10%, 1206| Murata, GRM31CR61A476KE15L
5| 1| U1| 5 A, ultra-low noise, high PSRR, 55 mV dropout, ultra-fast linear
regulator| Analog Devices, Inc., LT3078AV#PBF
Optional Evaluation Board Components| | | |
1| 1| C5| 220 μF capacitor, tantalum polymer, 10 V,| AVX, TCJD227M010R0040
| | | 20%, 7343, 40 mΩ ESR|
2| | C7, C8, C9, C10, C11,| Capacitors, 1206, optional| Optional
| | C12, C14, C15, CIN2| |
3| | C6, C13| Capacitors, 0603, optional| Optional
4| 1| C16| 4700 pF capacitor, X7R, 16 V, 10%, 0603| Kemet, C0603C472K4RACTU
5| 1| Q1| Transistor, N-Channel, 30 V, 75 A| Onsemi, FDMC8010
6| 1| R1| 51 kΩ resistor, 5%, 1/10 W, 0603, AEC-| Vishay, CRCW060351K0JNEA
| | | Q200|
7| 1| R2| 909 Ω resistor, 1%, 1/10 W, 0603, AEC-| Vishay, CRCW0603909RFKEA
| | | Q200|
8| 1| R3| 2 kΩ resistor, 1%, 1/10 W, 0603, AEC-| Vishay, CRCW06032K00FKEA
| | | Q200|
9| | R4| Resistor, 2512, optional| Optional
10| 1| R5| 0.02 Ω resistor, 1%, 1 W, 2010| Vishay, WSLT2010R0200FEB18
11| 1| R6| 10 kΩ resistor, 5%, 1/10 W, 0603| Yageo, RC0603JR-0710KL
Hardware| | | |
1| 8| E1 to E8| Test points, turret, 0.094″ PBF| Mill-Max,
2501-2-00-80-00-00-07-0
2| 5| J1, J2, J6, J7, J9| Connectors, banana jack, female,| Keystone, 575-4
| | | through-hole, non-insulated, swage,|
| | | 0.218″|
3| 3| J3 to J5| Connectors, RF, BNC, receptacle, jack,| Amphenol RF, 112404
| | | 5-pin, straight, through-hole, 50 Ω|
4| 1| JP1| Connector, header, male, 1 x 3, 2 mm,| Wurth Elecktronik,
62000311121
| | | vertical, straight, through-hole|
5| 4| JP2 to JP4, JP6| Connectors, header, male, 1 x 4, 2 mm,| Wurth
Elecktronik, 62000411121
| | | vertical, straight, through-hole|
6| 1| JP5| Connector, header, male, 2 × 3, 2 mm,| Wurth Elecktronik,
62000621121
| | | vertical, straight, through-hole|
7| 4| MP1 to MP4| Standoffs, nylon, snap-on, 1/2 inch| Wurth Elecktronik,
702935000
8| 6| XJP1 to XJP6| Connector shunt, female, 2-position, 2| Wurth Elecktronik,
60800213421
| | | mm|
1 Blank cell is for optional components.
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit
boards can discharge without detection. Although this product features
patented or proprietary protection circuitry, damage may occur on devices
subjected to high energy ESD. Therefore, proper ESD precautions should be
taken to avoid performance degradation or loss of functionality.
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