ADMV8052 30 MHz to 520 MHz Digitally Tunable Band Pass Filter

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Product Information

Specifications

• Product Name: ADMV8052
• Frequency Range: 30 MHz to 520 MHz
• Interface: SPI (4-wire serial port interface)
• Software: ACE software
• Power Supply: 5V USB

Product Usage Instructions

Evaluation Board Hardware

The ADMV8052-EVALZ features the ADMV8052 chip, a negative
voltage generator, and three LDO regulators. These regulators are
powered by the 5V USB supply voltage from the PC via the SDP-S
connector.

Lab Bench Setup

To observe the filter response, connect RF1 and RF2 ports to a
network analyzer. Typically, RF1 and RF2 are connected to Port 1
and Port 2 on the network analyzer.

Evaluation Board Software

Installing ACE Software, ADMV8052 Plug-Ins, and Drivers

1. Visit the ACE software page for installation instructions.

2. If ACE software is already installed, ensure it is the latest
   version.

3. To update ACE software:

4. Uninstall the current version.

5. Delete the ACE folder in C:ProgramDataAnalog Devices and
   C:Program Files (x86)Analog Devices.

6. Install the latest version of ACE software.

FAQ

Q: What is the frequency range of the ADMV8052?

A: The ADMV8052 operates in the frequency range of 30 MHz to 520
MHz.

Q: How is the ADMV8052 powered?

A: The ADMV8052 is powered by the 5V USB supply voltage from the
PC via the SDP-S connector.

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EVAL-ADMV8052 User Guide
UG-1951
One Technology Way · P.O. Box 9106 · Norwood, MA 02062-9106, U.S.A. · Tel: 781.329.4700 · Fax: 781.461.3113 · www.analog.com

Evaluating the ADMV8052 30 MHz to 520 MHz, Digitally Tunable Band-Pass Filter

FEATURES
Fully featured evaluation board for the ADMV8052 On-board SDP-S connector for the SPI Evaluation using on-board LDO regulators powered by the USB ACE software interface for SPI control
EQUIPMENT NEEDED
Network analyzer Windows® PC USB cable EVAL-SDP-CS1Z (SDP-S) controller board
DOCUMENTS NEEDED
ADMV8052 data sheet
SOFTWARE NEEDED
ACE software
GENERAL DESCRIPTION
The ADMV8052-EVALZ is available for evaluating the ADMV8052 digitally tunable, band-pass filter (BPF). The ADMV8052-EVALZ incorporates the ADMV8052 chip, as well as a negative voltage generator, low dropout (LDO) regulators, and an interface to the EVAL-SDP-CS1Z (SDP-S) system demonstration platform (SDP) to allow simple and efficient evaluation. The negative voltage generator and LDO regulators allow the ADMV8052 to be powered by either the 5 V USB supply voltage from the PC via the SDP-S or by using two external power supplies.
The ADMV8052 is an IC that features a digitally selectable frequency of operation. The chip features three BPFs that span from 30 MHz to 520 MHz. The chip can be programmed using a 4-wire serial port interface (SPI), and the SDP-S controller allows the user to interface with the SPI of the ADMV8052 through the Analog Devices, Inc., Analysis | Control | Evaluation (ACE) software.
For full details on the ADMV8052, see the ADMV8052 data sheet, which must be consulted in conjunction with this user guide when using the ADMV8052-EVALZ.

EVALUATION BOARD PHOTOGRAPH
Figure 1.

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PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS.

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TABLE OF CONTENTS
Features …………………………………………………………………………………. 1 Equipment Needed………………………………………………………………… 1 Documents Needed ……………………………………………………………….. 1 Software Needed ……………………………………………………………………. 1 General Description ………………………………………………………………. 1 Evaluation Board Photograph………………………………………………… 1 Revision History ……………………………………………………………………. 2 Evaluation Board Hardware …………………………………………………… 3 Evaluation Board Software …………………………………………………….. 4
Installing the ACE Software, ADMV8052 Plug-Ins, and Drivers……………………………………………………………………………….. 4 Plug-In Overview ………………………………………………………………. 5 Plug-In Details …………………………………………………………………… 6 Performing Evaluation …………………………………………………………. 10
REVISION HISTORY
2/2024–Revision 0: Initial Version

EVAL-ADMV8052 User Guide
ADMV8052-EVALZ Quick Start ……………………………………… 10 Network Analyzer Settings ………………………………………………. 10 CSV Files …………………………………………………………………………. 10 Automatic Chip Reset………………………………………………………. 11 Manual Chip Reset…………………………………………………………… 11 Loss of Board Communication ………………………………………… 11 Regulator Bypass ……………………………………………………………… 11 Plug-In SPI Register Controller………………………………………… 12 Evaluation Board Schematics and Artwork ………………………….. 13 ADMV8052-EVALZ ………………………………………………………… 13 Ordering Information ………………………………………………………….. 17 Bill of Materials………………………………………………………………… 17

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EVAL-ADMV8052 User Guide

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EVALUATION BOARD HARDWARE
The ADMV8052-EVALZ has the ADMV8052 chip on board. The ADMV8052-EVALZ also includes a negative voltage generator and three LDO regulators to provide the necessary supply voltages for the chip. The regulators can be entirely powered by the 5 V USB supply voltage from the PC via the SDP-S.
To power the ADMV8052-EVALZ using the 5 V USB supply, slide the S1 switch down (as shown in Figure 2) to power the on-board negative voltage generator and LDO regulators. Alternatively, the ADMV8052-EVALZ can be powered externally by sliding the S1 switch up and then connecting the power supplies to the VPOS and VNEG Subminiature Version A (SMA) ports or test points. The applicable voltage range for the positive input VPOS is between 3.5 V and 5.5 V, and the applicable voltage range for the negative input VNEG is between -5.5 V and -2.7 V.

Figure 2 shows an example lab bench setup for the ADMV8052EVALZ. To observe the filter response from the ADMV8052EVALZ, connect the RF1 and RF2 ports to a network analyzer (or similar instrument). Typically, RF1 and RF2 are connected to Port 1 and Port 2 on the network analyzer, as shown in Figure 2.

NETWORK ANALYZER

PORT 1

PORT 2

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S1
Figure 2. Lab Bench Setup
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EVALUATION BOARD SOFTWARE
INSTALLING THE ACE SOFTWARE, ADMV8052 PLUG-INS, AND DRIVERS
The ADMV8052-EVALZ uses the Analog Devices ACE software. For instructions on how to install and use the ACE software, go to the ACE software page.
If the ACE software is already installed on the PC, ensure that the installed ACE software is the latest version, as listed on the ACE software page. If the installed software is not the latest version, take the following steps to install the updated ACE software:
1. Uninstall the current version of the ACE software on the PC. 2. Delete the ACE folder found in C:ProgramDataAnalog
Devices and C:Program Files (x86)Analog Devices. 3. Install the latest version of the ACE software. During the
installation, ensure that the .NET 40 Client, SDP Drivers, and LRF Drivers components are selected (see Figure 3).

EVAL-ADMV8052 User Guide
Once the installation finishes, the ADMV8052 Board plug-in appears in the Attached Hardware section of the Start tab when the ACE software is running. (see Figure 4).

Figure 4. ADMV8052 Board Plug-In Window after Opening the ACE Software

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Figure 3. Required Driver Installations with the ACE Software

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EVAL-ADMV8052 User Guide
PLUG-IN OVERVIEW
When the ADMV8052-EVALZ is connected to the PC, the ADMV8052 Board appears in the Attached Hardware section of the Start tab. Double-click the ADMV8052 Board plug-in to open two tabs, which are the ADMV8052 Board plug-in view (see Figure 5) and the ADMV8052 chip plug-in view (see Figure 6), respectively.
The ADMV8052 chip plug-in view includes the following feature sections (see Table 1 for additional information on these sections):
· The CONFIGURATION section (load from .csv) · The Logic Pins section · The SFL Settings section · The chip Status section · The Display controls section · The Filter Settings section
The ACE software provides a simple tutorial for testing the ADMV8052. For a more customized and detailed implementation, refer to ADMV8052 data sheet for a full description of the functionality, registers, and corresponding settings.

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Figure 5. ADMV8052 Board Plug-In View Figure 6. ADMV8052 Chip Plug-In View

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PLUG-IN DETAILS
The full screen ADMV8052 chip plug-in with labels is shown in Figure 7. The labels correspond to items listed in Table 1, which describes the functionality of each section. For additional detailed programming, refer to the ADMV8052 data sheet.

EVAL-ADMV8052 User Guide

J1

J2

J3

J4

J5

J6

A

B

C

E

F

D L

G H
K

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Figure 7. ADMV8052 Chip Plug-In with Labels

Table 1. ADMV8052 Block Diagram Label Functions (See Figure 7)

Label

Function

A

Use the CONFIGURATION section to initialize the ADMV8052-EVALZ.

Load Settings from CSV: click the … button to select which .csv file to load into the CONFIGURATION section.

Check to Load Settings: once a file is selected, select this check box to load the .csv file contents into the CONFIGURATION section. Note that a check mark does not appear when the check box is selected.

Filter Configuration: select the configuration settings for interpolation, tracking, or debug.

Switch Settings: select the switch position settings for SPI write mode.

Center Frequency Settings: select the center frequency settings for SPI write mode.

Bandwidth Settings: select the bandwidth settings for SPI write mode.

Match Settings: select the match settings for SPI write mode.

SFL Settings: select the SPI fast latch (SFL) settings that are used when the chip is placed into the SPI fast latch mode.

Lookup Table 0 to 15: define the configuration for lookup table (LUT)0 to LUT15.

Lookup Table 16 to 31: define the configuration for LUT16 to LUT31.

Lookup Table 32 to 47: define the configuration for LUT32 to LUT47.

Note that following functions are not shown in Figure 7. Scroll down in the CONFIGURATION section to view these functions.

Lookup Table 48 to 63: define the configuration for LUT48 to LUT63.

Lookup Table 64 to 79: define the configuration for LUT64 to LUT79.

Lookup Table 80 to 95: define the configuration for LUT80 to LUT95.

Lookup Table 96 to 111: define the configuration for LUT96 to LUT111.

Lookup Table 112 to 127: define the configuration for LUT112 to LUT 127.

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EVAL-ADMV8052 User Guide

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Label
B C D E

Function
Band 1 Coefficients: define the interpolation coefficients for Band 1. Band 2 Coefficients: define the interpolation coefficients for Band 2. Band 3 Coefficients: define the interpolation coefficients for Band 3. Summary: click this button to review the settings for the initial setup. Apply: click this button to apply the settings to the chip. Note that clicking Apply Changes (J1) does not update the changes in this section. In addition, at startup, the main diagram user controls cannot be updated until the Apply button is clicked at least once. Restore Software Defaults: click this button to zero out the CONFIGURATION section prior to loading a different .csv file.
Use the SFL Settings section to configure the SPI fast latch settings on the chip when in the SFL mode. Refer to the ADMV8052 data sheet for more information regarding the internal state machine and SFL mode functionality. This section includes the following: FAST_LATCH_STATE: this value is the next state of the internal state machine pointer (read only). FAST_LATCH_START: this value determines the start location within the internal state machine. FAST_LATCH_STOP: this value determines the stop location within the internal state machine. FAST_LATCH_DIRECTION: this bit determines the direction that the internal state machine advances for each rising edge of the CS pin when in SFL mode.
The Status section includes the following: Mode: when the SFL pin is low, the mode is SPI Write. When the SFL pin is high, the mode is SPI Fast Latch, and the chip uses the LUT. CSB_AUX Count: when in SFL mode, this field displays the number of times the SDP-S logic pin, CSB_AUX, was toggled. Message: upon entering SFL mode, the Message field displays Waiting for CSB. Once the CSB_AUX pin is toggled, the Message field displays the current LUT number followed by the next LUT number. The displayed block diagram section shows the position of the switch and capacitor codes for each filter band within the chip. While in SPI Write mode, any changes to the WRx registers automatically trigger a read operation of the READBACK registers, so that this section always reflects the actual hardware.
The Filter Settings section shows several controls for configuring each filter band in the chip. Depending upon if INTERPOLATE is enabled, various controls can be visible. When INTERPOLATE is enabled (as shown in Figure 7), the following controls are visible: Band Selection: this numeric up and down box (0 to 3) is used to set the desired filter band. A value of 0 corresponds to the bypass configuration, and all other values correspond to the filter band number. FC_LOAD Value: this numeric up and down box (0 to 255) is used to set the desired center frequency value. Note that this is a unitless quantity, where a 0 corresponds to the lowest center frequency within a particular band, and 255 corresponds to the highest center frequency within a particular band. Requested FC: enter in a requested center frequency in this text box. The value entered is used to select the desired band of operation and compute the closest FC_LOAD Value for that frequency of operation. Anticipated FC: this text box is an estimation of the operating center frequency based upon the FC_LOAD Value. Switch Set: this check box determines if the input and output switches change. INTERPOLATE: this check box enables the interpolation functionality on the chip. TRACK: this check box enables filter tracking, whereby when the capacitor codes of one filter are changed, the other two nonselected filter capacitor codes are also set to the same values. When INTERPOLATE is disable (not shown in Figure 7), the following controls are visible: Band Selection: this numeric up and down box (0 to 3) is used to set the desired filter band. A value of 0 corresponds to the bypass configuration, and all other values correspond to the filter band number. FC_LOAD Value: this numeric up and down box (0 to 255) is used to set the desired center frequency capacitor code. BW_LOAD Value: this numeric up and down box (0 to 255) is used to set the desired bandwidth capacitor code. MATCH_LOAD Value: this numeric up and down box (0 to 255) is used to set the desired input and output match capacitor code. Switch Set: this check box determines if the input and output switches change. INTERPOLATE: this check box enables the interpolation functionality on the chip. TRACK: this check box enables filter tracking, whereby when the capacitor codes of one filter are changed, the other two nonselected filter capacitor codes are also set to the same values. READBACK Values –> Filter Settings: this button is available when interpolation is disabled. Click this button to populate the read back values from the hardware into the FC_LOAD, BW_LOAD, and MATCH_LOAD values.

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EVAL-ADMV8052 User Guide

Label F
G
H K J1 J2 J3 J4 J5 J6 L

Function
The Display section determines the actively selected WR or LUT number. This section includes the following:
Mode: use the drop-down menu to select either Write or LUT display mode.
WR: when the Mode is set to Write, scroll up and down to set the WR number (0 to 3) that is currently being configured and displayed in the Filter Settings section. Changing the WR number automatically changes the Mode to Write.
LUT: when the Mode is set to LUT, scroll up and down to set the LUT number (0 to 127) that is currently being configured and displayed in the Filter Settings section. Changing to the LUT number automatically changes the Mode to LUT.
Use the Logic Pins section to toggle the SDP-S logic pins, which are connected to the logic pins on the ADMV8052 chip. This section includes the following:
RSTB: clear the check box to bring the ADMV8052 RST pin low, which holds the chip in reset. Select the check box again to bring the chip out of reset.
SFL: select the check box to bring the ADMV8052 SFL pin high, which places the chip in SFL mode. This action also toggles the on-board ADG749BKSZ switch connected to the ADMV8052 CS pin (see Figure 11). While in SFL mode, the ADMV8052 CS pin is connected to the SDP-S logic pin, CSB_AUX, and normal SPI transactions are disallowed.
CSB_AUX: this pin is only available in SFL mode. Selecting the check box brings the CSB_AUX pin high, which advances the internal state machine pointer to the next LUT. If an external waveform generator is connected to the CSB_EXT port on the ADMV8052-EVALZ, the CSB_AUX pin has no effect, and the CSB_EXT port takes precedence.
Use the Click to Enable Auto Apply button to toggle the ADMV8052 Board plug-in Auto Apply feature. This feature is useful for quickly enabling auto apply so that any change made to the chip settings are automatically sent to the ADMV8052-EVALZ. Once the button is clicked, the Click to Disable Auto Apply button appears.
Click Proceed to Memory Map to open the ADMV8052 Memory Map (see Figure 8).
All changes, except those made within the CONFIGURATION section, do not take effect until clicking Apply Changes. If Auto Apply is highlighted in the ADMV8052 Board tab (see Figure 5), the Apply Changes feature continuously runs every few seconds, and users do not have to click Apply Changes to apply or read back the block diagram settings.
To read back all of the SPI registers of the chip, click Read All.
Click Reset Chip to reset the chip.
Click Diff to show registers that are different on the chip.
Click Software Defaults to restore the software defaults to the chip, and then click Apply Changes. The software defaults for the ADMV8052 are for all registers to be zero, except for Register 0x011, which is set to 0x7F, and the interpolation coefficients in Register 0x300 to Register 0x32F.
Click Memory Map Side-By-Side to enable the side by side memory map view.
Click Interpolation Values to open the subdiagram for displaying and editing the interpolation coefficients (see Figure 9). The interpolation coefficients can be changed to calibrate the center frequency and/or change the desired operating bandwidth for each filter band. Refer to the ADMV8052 data sheet for guidance on editing the interpolation coefficients.

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EVAL-ADMV8052 User Guide

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Figure 8. ADMV8052 Memory Map in the ACE Software Figure 9. Interpolation Values Subdiagram in the ACE Software
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PERFORMING EVALUATION
ADMV8052-EVALZ QUICK START
To set up the ADMV8052-EVALZ, take the following steps:
1. Connect the RF1 and RF2 ports to a network analyzer (or a similar instrument). Typically, RF1 and RF2 are connected to Port 1 and Port 2 on the network analyzer, as shown in Figure 2.
2. Connect the SDP-S to the 120-pin connector on the ADMV8052-EVALZ. Do not connect the SDP-S to the PC until after completing Step 3 or Step 4.
3. On the ADMV8052-EVALZ, slide the S1 switch down (as shown in Figure 2) to power the ADMV8052-EVALZ from the 5 V USB supply voltage from the PC via the SDP-S.
4. Alternatively to Step 3, slide the S1 switch up and connect the power supplies to the VPOS and VNEG ports. The applicable voltage range for VPOS is between +3.5 V and +5.5 V and for VNEG is between -5.5 V and -2.7 V. The external supply current limits must be set to 20 mA. Expected supply current drawn for VPOS is 12 mA to 14 mA and for VNEG is 2 mA to 3 mA. The ADMV8052 chip current drawn per supply pin is typically 10s of microamps or less. Most of the current drawn from the ADMV8052EVALZ comes from the LDO regulators and the status indicator light emitting diodes (LEDs), DS1 to DS3.
5. Connect a USB cable between the PC and the SDP-S. 6. Open the ACE software. The ADMV8052 Board appears
in the Attached Hardware section of the Start tab. Double-click the ADMV8052 Board plug-in to open two tabs, one is the ADMV8052 Board plug-in view and one is the ADMV8052 chip plug-in. 7. Use the CONFIGURATION section (see Figure 10) in the ACE software to initialize the chip. By default, the ADMV8052_Register_Load_BW9.csv file is loaded into this section. Click Apply to send the default settings to the chip and to allow the main diagram user controls to become editable.
NETWORK ANALYZER SETTINGS
When evaluating the ADMV8052-EVALZ, a good starting point for configuring the network analyzer is as follows:
· Start frequency = 0.01 GHz · Start frequency = 1.01 GHz · Number of points = 1001 · Step size = 1 MHz · Power level = -10 dBm · Measure types = S-parameters (S21, S11, and S22) · Format = log magnitude (S21), smith charts (S11 and S22) · Calibration = full 2-port

EVAL-ADMV8052 User Guide
Figure 10. ADMV8052 CONFIGURATION Section
CSV FILES
By default, the ADMV8052_Register_Load_BW9.csv file is loaded into the CONFIGURATION section. This file contains interpolation coefficients that correspond to approximately 9% bandwidth. There are two additional .csv files provided that contain interpolation coefficients for 7% and 11% bandwidth, respectively. To load a different .csv file in the CONFIGURATION section, take the following steps: 1. If the Modify button is visible, click to allow changes. 2. Click Restore Software Defaults to zero out the
CONFIGURATION section. 3. Click the … button next to Load Settings from CSV to
select which .csv file to load (see Figure 10). 4. Select the Check to Load Settings check box to load the .csv
file contents into the CONFIGURATION section. Note that a check mark does not appear when the check box is selected. 5. Click Apply to send out the settings to the hardware.

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EVAL-ADMV8052 User Guide
AUTOMATIC CHIP RESET
If a reset of the ADMV8052 chip is required on the ADMV8052-EVALZ, click Reset Chip (see Figure 7 and Label J3 in Table 1 for additional information). This automated sequence performs the following actions:
· Toggles all SDP-S general-purpose input/output (GPIO) logic pins to a low state, which brings the RST pin of the ADMV8052 low to initiate a hard reset of the ADMV8052.
· Toggles the RST pin high to bring the ADMV8052 chip back to the normal operating state.
· Programs Register 0x000 to 0x81, which also resets the ADMV8052. This step covers legacy boards that did not have the RST pin connected.
· Programs Register 0x000 to 0x3C to enable the SDO pin on the ADMV8052 and to allow SPI streaming with Endian register ascending order.
· Reads back the register settings of the ADMV8052.
MANUAL CHIP RESET
For manual reset operations, the following outlines various ways to perform a reset:
· There is a reset button (S2) on the ADMV8052-EVALZ evaluation board. Pressing this button pulls the RST pin low to initiate a reset to the factory power-up state.
· The RST pin can also be pulled low from within the ACE software by unchecking the RSTB check box in the lower right corner of Figure 7 (see Label G). When using this option, be sure to click the check box again to return the RST pin high.
· Register 0x000 can be programmed to 0x81 to initiate a reset of the ADMV8052.
Regardless of the manual reset option used, it is recommended to perform the following after the device resets:
· Programs Register 0x000 to 0x3C to enable the SDO pin on the ADMV8052 and to allow SPI streaming with Endian register ascending order.
· Read back all registers on the ADMV8052.

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LOSS OF BOARD COMMUNICATION
When the ADMV8052 is turned off and then on, or if the USB cable is disconnected and connected while the ACE software is running, communication with the ADMV8052 may be lost. To regain communication, take the following steps:
1. Click the System tab. 2. Click the USB symbol in the SDP-S Controller subsystem. 3. Click Acquire.
If this action does not work, restart the ACE software to reinitiate communication with the ADMV8052-EVALZ.
REGULATOR BYPASS
The ADMV8052-EVALZ has a negative voltage generator and three LDO regulators on board that allow the user to operate the device using the 5 V USB supply voltage from the PC via the SDP-S. By default, the provisional 2.5 V LDO regulator U3 is not installed because the ADMV8052 has a built-in LDO regulator for that supply voltage. The other two on-board LDO regulators, U2 and U5, provide the necessary supply voltages of +3.3 V and -2.5 V, respectively. If desired, these two LDO regulators can be bypassed by removing the 0 resistors (R23 and R32) from the ADMV8052-EVALZ and then by applying each voltage independently by using the corresponding test points. Bypassing the on-board regulators is useful for measuring the ADMV8052 supply current, but it must be noted that each supply pin is also connected to status indicator LEDs, DS1 to DS3, and each LED draws approximately 2 mA of current. Remove the R2, R3, and R91 resistors to disable these status indicators. See Figure 11 and Figure 12 for more details.

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PLUG-IN SPI REGISTER CONTROLLER
The ADMV8052 plug-in utilizes an SPI register controller to communicate with the ADMV8052. When using the ADMV8052 in a system, it is recommended to follow a similar methodology for implementing SPI communication. The following is a summary of the SPI register controller:
1. Determine if Register 0x000 is not set to 0x3C. 2. If Step 1 is true, set Register 0x000 to 0x3C to enable the
SDO pin on the ADMV8052 and to allow SPI streaming with Endian register ascending order. 3. Determine if the values have changed for any of the WRx registers (Register 0x020 to Register 0x02F). 4. If Step 3 is true, write Register 0x020 to Register 0x02F by pointing to Register 0x020 and streaming out 16 bytes of data. The transaction is 144 bits in total (R/W bit + 15 address bits + 128 data bits). Streaming out the data in this order ensures that the switch position priority is WR0 to WR3. 5. If Step 4 has occurred, write dummy data to Address 0x0A. Note that Address 0x0A does not exist in the ADMV8052, and the written dummy data is ignored. This step is microcontroller architecture dependent and can be ignored in most cases. It is necessary for the SDP-S to clear the SPI bus and reconfigure for a standard 24-bit SPI transaction.

EVAL-ADMV8052 User Guide
6. Determine if the values have changed for any of the LUT registers (Register 0x100 to Register 0x2FF).
7. If Step 6 is true, write to Register 0x100 to Register 0x2FF by performing the following:
· Pointing to Register 0x100 and streaming out 64 bytes of data.
· Pointing to Register 0x140 and streaming out 64 bytes of data.
· Pointing to Register 0x180 and streaming out 64 bytes of data.
· Pointing to Register 0x1C0 and streaming out 64 bytes of data.
· Pointing to Register 0x200 and streaming out 64 bytes of data.
· Pointing to Register 0x240 and streaming out 64 bytes of data.
· Pointing to Register 0x280 and streaming out 64 bytes of data.
· Pointing to Register 0x2C0 and streaming out 64 bytes of data.
8. If Step 7 has occurred, repeat Step 5. 9. Write out any remaining registers that may have changed.

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EVAL-ADMV8052 User Guide

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EVALUATION BOARD SCHEMATICS AND ARTWORK

ADMV8052-EVALZ

THRU1 1 DNI 234 142-0701-851

THRUCAL
50 TRACE LINE LENGTH SHALL BE SAME AS LAUNCHESTO/FROM RF1 AND RF2.

THRU2 DNI 1
43 2
142-0701-851

PAD16 GND
PAD15 GND
32 GND
31 GND
30 GND
29 GND
28 GND
27 GND
26 GND
PAD14 GND
PAD13 GND

1 RF1

2 34

50 TRACE

142-0701-851

S2

1

3

2

4

B3S-1000

RSTB

C14 0.1µF

PAD5 GND
PAD6 GND
10 SDI
11 SFL
12 GND
13 GND
14 GND
15 GND
16 VDD (+3.3V)
PAD7 GND
PAD8 GND

PAD1 PAD2

GND GND

1

GND

2

GND

3

GND

4

RF1

GND 5

RF1

6

RST

7

SCLK

8

CS

9

SDO

PAD3 GND
PAD4 GND

U1

ADMV8052ACCZ

PAD12 GND
PAD11 GND
25 GND
24 GND
23 GND
22 GND
21 RF2
20 GND
19 VSS (-2.5V)
18 BYP
17 GND
PAD10 GND
PAD9 GND

SCLK

R12

33

CSB_U1

SDO

R13

33

SDI

R14

33

SFL

R15

33

SFL R16 3P3VUSB
C15 0.1µF

33

1 IN 2 3 VDD
GND

U7
S2 6 D5 4
S1

ADG749BKSZ

R21 0
R17 33

CSB_U1
R40 0 DNI
CSB

C81 10pF DNI

R1

CSB_AUX

330

FOR 10MILTHK CORE LAYER USE

R81

1

142-0701-851

49.9

CSB_EXT 432

RF2

RF2 1

50 TRACE

432

142-0701-851

C3 100pF

C13 0.1µF

C1 100pF
2P5V
C4 47µF

N2P5V
C11 0.1µF PLACE SMALLER CAP AS CLOSE TO DUT AS POSSIBLE

PLACE SMALLER CAP AS CLOSE TO DUT AS POSSIBLE

C2 100pF

3P3V
C12 0.1µF

3P3V

2P5V

N2P5V

R91 750

R2 330

R3 330

A DS1 LTST-C190GKT
C

A DS2 LTST-C190GKT
C

C
DS3 LTS T-C190GKT A

Figure 11. ADMV8052-EVALZ Schematic, Page 1

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Figure 12. ADMV8052-EVALZ Schematic, Page 2 Rev. 0 | Page 14 of 18

REG_POS_IN

U2
ADP7156ACPZ-3.3-R7

C21 10µF

9

1

VIN

VOUT

10 VIN

VOUT 2

3

R22

0

5

VOUT_SENSE

EN

7

4 BYP

REF 6

8

REF_SENSE

VREG PAD

C31

C32

PAD

1µF

1µF

R41

0

DNI

R24
0 C33 1µF

C23 10µF
DNI

R25
C34 1µF DNI

U3
ADP7156ACPZ-2.5

9 10
0 DNI 5 4 8

VIN VIN
EN BYP VREG

1 VOUT VOUT 2
3 VOUT_SENSE
REF 7 6
REF_SENSE PAD

C35

DNI PAD

1µF

R42

DNI

0

DNI

R27
0 DNI C36
1µF DNI

R23
0 C22 10µF

3P3V RED

R43 0 DNI

R26

DNI

0 DNI

C24

10µF

DNI

2P5V RED

REG_POS_IN

R28

0

5VUSB DNI R44

0

FOR 10MILTHK CORE LAYER USE

VPOS

1

23 4

GND1

TP_VPOS

DNI R45

RED

0

S1

CL-SB-22A-11T

VIN_POS 5VUSB

1 2
3

VIN_NEG N2P7V

4 65

142-0701-851

BLK

FOR 10MILTHK CORE LAYER USE

VNEG

1

R46 DNI
0 DNI R47
0

23 4 142-0701-851

BLU TP_VNEG

REG_POS_IN REG_NEG_IN

S1 CONFIGURATION

U4 LT1617ES5-1#PBF

5 V IN
4 SHDN

1 SW
3 NFB

C25 10µF

GND 2

NFB

L1 22UH COILCRAFT LPD5030-223MRC

2

3

1

4

C37
1µF C0402

A C D1
BAT54H,115

REG_NEG_IN

C27 10µF C0603

R31 0
DNI R50 100k C17

3P3V 2P5V

TWI_A0
R54 100k

3P3VUSB

R52 100k DNI
SCL_SDP R53 100k

C16 0.1µF

8

U6

1 A0 VCC

2 A1

3 A2

SDA 5

6 SCL

7 WP VSS

SDA_SDP

4 24LC32A-I/MS

TWI_A0

CSB_AUX RSTB

R11 330

R61 29.4k

R29
0 C26 10µF C0603

R30
0 C18 0.1µF DNI

C19 0.1µF DNI

N2P7V
R49 100k DNI

NFB

R71 24.9k

R33
5VUSB 0

DNI R48 0

U5
ADP7183ACPZN2.5-R7

8 2 3 5 4 7 PAD

VIN

SENSE

VA

1

EN

VOUT

VAFB

VREG

EP GND

C39

6

1µF

R32
0 C28 10µF

N2P5V BLU
N2P5V
GND2 BLK

P2
1 2 3 4 5 6 7 8 9 10
M20-9980546

R4

330

R5

330

R6

330

R7

330

R8

330

R9

330

R10 330

P1

60 RESET_IN_N

BMODE1 61

59

62

58 UART_RX

UART_TX 63

GND

GND

57 RESET_OUT_N

SLEEP_N 64

56

65

55 EEPROM_A0

WAKE_N 66

NC

NC

54 NC

NC 67

53

68

52 NC

NC 69

GND

GND

51 NC

NC 70

50

71

49 NC

CLKOUT 72

TMR_C

TMR_D

48 TMR_A

TMR_B 73

47

74

46 GPIO6

GPIO7 75

GND

GND

45 GPIO4

GPIO5 76

44

77

43 GPIO2

GPIO3 78

GPIO0

GPIO1

42 SCL_1

SCL_0 79

41

80

40 SDA_1

SDA_0 81

GND

GND

39 SPI_SEL1/SPI_SS_N

SPI_CLK 82

38

83

37 SPI_SEL_C_N

SPI_MISO 84

36 SPI_SEL_B_N

SPI_MOSI 85

GND

SPI_SEL_A_N

35 SERIAL_INT

GND 86

34

87

33 SPI_D3

SPORT_TSCLK 88

SPI_D2

SPORT_DT0

32 SPORT_DT1

SPORT_TFS 89

31

90

30 SPORT_DR1

SPORT_RFS 91

SPORT_TDV1

SPORT_DR0

29 SPORT_TDV0

SPORT_RSCLK 92

28

93

27 GND

GND 94

PAR_FS1

PAR_CLK

26 PAR_FS3

PAR_FS2 95

25

96

24 PAR_A1

PAR_A0 97

PAR_A3

PAR_A2

23 GND

GND 98

22

99

21 PAR_CS_N

PAR_INT 100

PAR_RD_N

PAR_WR_N

20 PAR_D1

PAR_D0 101

19

102

18 PAR_D3

PAR_D2 103

PAR_D5

PAR_D4

17 GND

GND 104

16

105

15 PAR_D7

PAR_D6 106

PAR_D9

PAR_D8

14 PAR_D11

PAR_D10 107

13

108

12 PAR_D13

PAR_D12 109

PAR_D14

GND

11 GND

PAR_D15 110

10

111

9 PAR_D17

PAR_D16 112

PAR_D19

PAR_D18

8 PAR_D21

PAR_D20 113

7

114

6 PAR_D23

PAR_D22 115

5 GND

GND 116

USB_VBUS

VIO

4 GND

GND 117

3

118

2 GND

GND 119

NC

NC

1 VIN

NC 120

FX8-120S-SV(21)

SDI SFL
SDO
CSB CSB_AUX SCLK 3P3VUSB RSTB

SFL

SCLK

SDO

C82 10pF
DNI

C8 10pF DNI

EXTERNAL SUPPLIES POWER BY USB

SLIDE UP SLIDE DOWN

0.1µF
C38 1µF

R51 100k DNI

SFL SCL_SDP SDA_SDP
SCLK SDO SDI CSB

R34 3P3VUSB
0

SDI
C84 10pF DNI

CSB
C85 10pF DNI

C86 10pF
DNI

26168-012

EVAL-ADMV8052 User Guide

UG-1951

EVAL-ADMV8052 User Guide

UG-1951

26168-013 26168-014

Figure 13. ADMV8052-EVALZ Layer 1

Figure 14. ADMV8052-EVALZ Layer 2

Rev. 0 | Page 15 of 18

UG-1951

EVAL-ADMV8052 User Guide

26168-015 26168-016

Figure 15. ADMV8052-EVALZ Layer 3

Figure 16. ADMV8052-EVALZ Layer 4

Rev. 0 | Page 16 of 18

EVAL-ADMV8052 User Guide

UG-1951

ORDERING INFORMATION

BILL OF MATERIALS

Table 2. ADMV8052-EVALZ Qty. Reference Designator 3 2P5V, 3P3V, TP_VPOS 2 GND1, GND2 2 N2P5V, TP_VNEG 5 CSB_EXT, RF1, RF2,
VNEG, VPOS 3 C1 to C3 7 C11 to C17 6 C21, C22, C25 to C28 6 C31 to C33, C37 to C39 1 C4 1 D1 3 DS1 to DS3 1 L1 1 P1
1 P2 11 R1 to R11 6 R12 to R17 11 R21 to R24, R28 to R34 2 R53, R54 1 R61 1 R71 1 R81 1 R91 1 S1 1 S2 1 U1 1 U2
1 U4 1 U5
1 U6 1 U7
2 C18, C19
2 C23, C24 3 C34 to C36 6 C81 to C86 12 R25 to R27, R40 to R48 4 R49 to R52 1 U3
2 THRU1, THRU2

Description Test points, red Test points, black Test points, blue Connectors, edge launch, SMA
Capacitors, 100 pF, 50 V, 5%, 0402 Capacitors, 0.1 µF, 16 V, 5%, 0402 Capacitors, 10 µF, 16 V, 10%, 0603 Capacitors, 1 µF, 16 V, 20%, 0402 Capacitor, 47 µF, 6.3 V, 20%, 0603 Diode, BAT54H, 30 V, SOD123F LED, LTST- C190GKT, green, 0603 Coupled inductor, 22 µH, 20% Connector, vertical, surface-mount technology (SMT), 120-pin Connector, vertical, header, 10-pin Resistors, 330 , 1/10 W, 5%, 0402 Resistors, 33 , 1/10 W, 1/%, 0402 Resistors, 0 , 1/16 W, 0402 Resistors, 100 k, 1/16 W, 5%, 0402 Resistor, 29.4 k, 1/10 W, 1%, 0402 Resistor, 24.9 k, 1/10 W, 1%, 0402 Resistor, 49.9 , 1/10 W, 1%, 0402 Resistor, 750 , 1/10 W, 5%, 0402 Switch, mechanical, slide, DPDT, 0.2 A Switch, mechanical, push button 30 MHz to 520 MHz, digitally tunable BPF 1.2 A, ultralow noise, high power supply rejection ratio (PSRR), fixed output, RF linear regulator, 3.3 V Micropower inverting dc-to-dc converter -300 mA, ultralow noise, high PSRR, low dropout linear regulator, -2.5 V IC, 24LC32A, EEPROM, I2C CMOS, 1.8 V to 5.5 V, 2.5 , 2:1 mux/SPDT switch in SC70 package Capacitors, 0.1 µF, 16 V, 5%, 0402, do not install (DNI) Capacitors, 10 µF, 16 V, 10%, 0603, DNI Capacitors, 1 µF, 16 V, 20%, 0402, DNI Capacitor, 10 pF, 50 V, 5%, 0402, DNI Resistors, 0 , 1/16 W, 0402, DNI Resistors, 100 k, 1/16 W, 5%, 0402, DNI 1.2 A, ultralow noise, high PSRR, fixed output, RF linear regulator, 2.5 V, DNI Connectors, edge launch, SMA, DNI

Manufacturer Components Corporation Components Corporation Components Corporation Cinch Connectivity
Johanson Dielectrics Kemet Murata Murata Murata NXP Semiconductor Lite-On Technology Coilcraft Hirose Electric Co.
Harwin, Inc. Panasonic Panasonic Stackpole Yageo Panasonic Panasonic Panasonic Panasonic Nidec Copal Electronics Omron Electronics Inc. Analog Devices Analog Devices
Analog Devices Analog Devices
Microchip Technology Analog Devices
Kemet
Murata Murata Yageo Stackpole Yageo Analog Devices
Cinch Connectivity

Part Number TP-104-01-02 TP-104-01-00 TP-104-01-06 142-0701-851
500R07N101JV4T C0402C104J4RACTU GRM188R61C106KAALD GRM155R61C105MA12D GRM188R60J476ME15D BAT54H,115 LTST-C190GKT LPD5030-223MRC FX8-120S-SV(21)
M20-9980546 ERJ-2GEJ331X ERJ-2RKF33R0X RMCF0402ZT0R00 RC0402JR-07100KL ERJ- 2RKF2942X ERJ-2RKF2492X ERJ-2RKF49R9X ERJ-2GEJ751X CL-SB-22A-11T B3S1000 ADMV8052ACCZ ADP7156ACPZ-3.3-R7
LT1617ES5-1#PBF ADP7183ACPZN2.5-R7
24LC32A-I/MS ADG749BKSZ
C0402C104J4RACTU
GRM188R61C106KAALD GRM155R61C105MA12D CC0402JRNPO9BN100 RMCF0402ZT0R00 RC0402JR-07100KL ADP7156ACPZ-2.5-R7
142-0701-851

Rev. 0 | Page 17 of 18

UG-1951 NOTES

EVAL-ADMV8052 User Guide

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.
©2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
UG26168-2/24(0)
Rev. 0 | Page 18 of 18

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