ReflexCES XpressSX AGI-FH400G Full Height Half Length Pcie Gen5 Network Processing Board Installation Guide
- June 13, 2024
- ReflexCES
Table of Contents
ReflexCES XpressSX AGI-FH400G Full Height Half Length Pcie Gen5 Network Processing Board Installation Guide
Full Specifications
*Use of CXLTM features might require separate CXLTM IP license purchase. Please contact Intel® for details. 2/5
Additional PCIe Gen4 x16 daughter
The XpressSX AGI-FH400G board needs to be inserted in a PCIe Gen5 compatible
server in order to deliver the full PCIe Gen5 x16 performances.
In case the user is only using a PCIe Gen4 compatible server, the XpressSX
AGI-FH400G is delivered with this PCIe Gen4 x16 daughter card. This way, the
system will achieve 2x Gen4 x16 performances similar to PCIe Gen5 x16, using
two R-Tile PCIe Hard IPs inside the FPGA.
The daughter card also supports x8x8 bifurcation mode.
Deliverables
- Full height half length 2-slot PCIe board with active heatsink and PCIe bracket
- 2x DDR4 SO-DIMM 32GByte each
- Board Support Package: Manuals, 2D drawing, HDL reference designs (Contact REFLEX CES for PCIe Gen5 CXLTM interface validation)
- DWF/STEP models (upon request)
- Online support at support.reflexces.com
- NDK package (including DPDK NIC application) provided separately by BrnoLogic
- 2x HSI cables (ARC6-16-10.0-LU-LD-2-1) and 1x USB-C to USB-C cables (0.72ft), 3.1 Gen2 to connect the PCIe Gen4 x16 daughter card
- PCIe Gen4 x16 daughter card
Ordering information
XpressSXAGI-FH400GT-ES = Intel® AgilexTM SoC I-Series ES Silicon
(AGIB027R29A1E2VR3), 3 banks DDR4 – No SoC support
XpressSXAGI-FH400GT = Intel® AgilexTM SoC I-Series Production Silicon
(AGIB027R29A1E2V), 3 banks DDR4
Contact sales for availability and pricing
Development Framework for High-speed Packet Processing
Start your design from standard NIC
- Provided as a free demo application
- Network module based on F-Tile 400G Ethernet Hard IP
- Ultra fast DMA with 400 Gbps throughput based on PCIe Gen5 x16 interface (R-Tile)
- Easy to use memory interface for single read/write data from/to card
- Preconfigured DDR4 controller for memory access from the user logic
- Precise timestamps with 2.5 ns resolution for 400G Ethernet
Easy to use NDK Development Framework
- Set of open-source IP cores for data manipulation
- Automatic scripts for complete design synthesis
- Single make command to create complete FPGA bitstream
- Bitstream identification through Device Tree ROM
- Easy to use software stack in a single RPM package
- Linux kernel driver, DPDK support, user space library, tools for the configuration of components
- Easy creation of custom application by user-friendly API for component access and DMA transfers
- Fully parameterizable and modular hardware and software architecture
Part number: NDK-PROF-SUPPORT
Target Network Applications
Hardware acceleration of precise network monitoring, IDS/IP systems, next
generation firewalls, test equipment, Anti DDoS and other time-critical
networking applications.
Only one card for 10, 40, 100, 200 and 400 GE link speeds.
Security devices
- Hardware filters and pattern matching to accelerate IDS/IPS systems
- Precise packet filtering and packet capture for lawful interception
- Anti DDoS with hardware IP or flow filtering controlled by software
Network monitoring probes
- High-speed packet capture with up to 512 receive queues, DPDK support
- Extraction of features for encrypted traffic analysis
- Variety of packet classification engines with wire-speed performance:
▪ TCAM with up to 512 general rules, each defined with individual wildcard mask
▪ Longest Prefix Match in deep pipeline with capacity for up to 100k prefixes
▪ Exact Match hash table with support for up to a million unique keys
▪ DDR/QDR/HBM based connection tables with tens of millions flow records
Design services
The card is prepared for custom hardware acceleration in FPGA
We provide FPGA design based on high-speed 400 Gb IP cores for:
- packet headers parsing (Ethernet, ICMP, IPv4, IPv6, MPLS, etc.),
- packet filtering and classification,
- flow cache and connection tracking tables,
- fast pattern matching and
- many other IP cores for fast packet processing in deep pipelines.
Contact information
sales@brnologic.cz
www.brnologic.cz
Open source IP library www.liberouter.org/ndk
© reflex ces 2023-All Rights Reserved Jan/v4.2
References
- Úvod | BrnoLogic
- Network Development Kit | Liberouter / Cesnet TMC group
- Embedded FPGA Solutions - reflex ces